公开(公告)号：US06782486B1

公开(公告)日：2004-08-24

申请号：US09637178

申请日：2000-08-11

Applicant: Paul C. Miranda ,  Brian D. McMinn

Inventor： Paul C. Miranda ,  Brian D. McMinn

IPC: G06F110

CPC classification number: H03L7/00 ,  G06F1/10

Abstract: An efficient clock start and stop apparatus for clock forwarded system I/O. The apparatus may include a buffer coupled to receive incoming data from a data source. The buffer is clocked by a first clock signal that is provided by the data source. The buffer is configured to store the incoming data in a plurality of sequential lines in response to the first clock signal. The buffer may be further configured to store a plurality of bits in a plurality of occupied-bit registers. Each one of the plurality of occupied-bit registers indicates that data is present in a corresponding sequential line in the buffer. The apparatus may further include a clock gate circuit coupled to the buffer and configured to provide a second clock signal. The clock gate circuit may be further configured to start the second clock signal when valid data is present in the buffer and to stop the second clock signal when no data is present in the buffer.

Abstract translation: 用于时钟转发系统I / O的高效时钟启动和停止装置。 该装置可以包括被耦合以从数据源接收输入数据的缓冲器。 缓冲器由数据源提供的第一个时钟信号计时。 缓冲器被配置为响应于第一时钟信号将输入数据存储在多个顺序行中。 缓冲器还可以被配置为在多个占用位寄存器中存储多个位。 多个占用位寄存器中的每一个指示数据存在于缓冲器中的对应的顺序行中。 该装置还可以包括耦合到缓冲器并被配置为提供第二时钟信号的时钟门电路。 时钟门电路还可以被配置为当缓冲器中存在有效数据时启动第二时钟信号，并且当缓冲器中没有数据时停止第二时钟信号。

公开(公告)号：US06718476B1

公开(公告)日：2004-04-06

申请号：US09724208

申请日：2000-11-27

Applicant: Hisato Shima

Inventor： Hisato Shima

IPC: G06F110

CPC classification number: G06F1/12 ,  H04J3/0679 ,  H04J3/0688

Abstract: A method of synchronizing each local clock to a master clock in a data bus system is described. In an embodiment, the data bus system includes a plurality of nodes each having a local clock. Initially, a clock source for each local clock is the respective local clock generator of each node. During formation of a data bus configuration for the data bus system, each node assigns either a first identifier or a second identifier to each port that is coupled to another port. If a node has a first identifier port, the node changes a clock source for its local clock from the local clock generator to a particular clock recovery circuit that is coupled to the first identifier port. In another embodiment, a clock source for each local clock is initially the respective multiple mode clock recovery circuit (MMCRC) operating in the unlocked mode. During formation of a data bus configuration for the data bus system, each node assigns either a first identifier or a second identifier to each port that is coupled to another port. If a node has a first identifier port, the node changes a clock source for its local clock from the MMCRC operating in the unlocked mode to the MMCRC operating in the locked mode, which is coupled to the first identifier port. The local clock of the root node serves as the master clock for synchronizing the local clocks of the other nodes.

Abstract translation: 描述了在数据总线系统中将每个本地时钟同步到主时钟的方法。 在一个实施例中，数据总线系统包括多个节点，每个节点具有本地时钟。 最初，每个本地时钟的时钟源是每个节点的相应本地时钟发生器。 在形成数据总线系统的数据总线配置期间，每个节点将第一标识符或第二标识符分配给耦合到另一个端口的每个端口。 如果节点具有第一标识符端口，节点将其本地时钟的时钟源从本地时钟发生器改变为耦合到第一标识符端口的特定时钟恢复电路。 在另一个实施例中，用于每个本地时钟的时钟源最初是处于解锁模式的相应的多模式时钟恢复电路（MMCRC）。 在形成数据总线系统的数据总线配置期间，每个节点将第一标识符或第二标识符分配给耦合到另一个端口的每个端口。 如果节点具有第一标识符端口，则节点将其本地时钟的时钟源从处于解锁模式的MMCRC更改为以锁定模式操作的MMCRC，该MMCRC耦合到第一标识符端口。 根节点的本地时钟作为主时钟，用于同步其他节点的本地时钟。

公开(公告)号：US06367026B1

公开(公告)日：2002-04-02

申请号：US09241325

申请日：1999-02-01

Applicant: Chen-Chi Chou ,  Jose L. Diaz

Inventor： Chen-Chi Chou ,  Jose L. Diaz

IPC: G06F110

CPC classification number: G06F1/10

Abstract: A method of and apparatus for providing clock signals for synchronizing operation of elements of a digital interface system between an IEEE 1394 serial bus and a personal computer interface (PCI) bus. The digital interface system includes a number of functional elements in addition to a PCI interface element. Each of the functional elements and the PCI interface element receives a system clock signal via a clock tree. The clock tree derives individual clock signals from the system clock and provides these individual clock signals to each of the functional elements. The clock tree is balanced such that each clock transition occurs at each of the functional elements, other than the PCI interface element, at substantially the same time. Clock balancing is achieved through appropriate circuit layout and insertion of delay elements. The clock tree also derives a clock signal for the PCI interface element from the system clock signal. The portion of the clock tree which provides this clock signal to the PCI interface is not balanced with respect to the remainder of the clock tree. Rather, this portion of the clock tree is conditioned to provide a minimum of delay so as to comply with timing requirements for the PCI bus, such as data set-up and hold times associated with transitions in this clock signal. Accordingly, portions of the clock tree are balanced while at least a portion of the clock tree is not balanced.

Abstract translation: 一种用于提供用于在IEEE 1394串行总线与个人计算机接口（PCI）总线之间的数字接口系统的元件的同步操作的时钟信号的方法和装置。 除了PCI接口元件之外，数字接口系统还包括许多功能元件。 每个功能元件和PCI接口元件经由时钟树接收系统时钟信号。 时钟树从系统时钟导出各个时钟信号，并将这些单独的时钟信号提供给每个功能元件。 时钟树是平衡的，使得每个时钟转换发生在除了PCI接口元件之外的每个功能元件的基本上相同的时间。 通过适当的电路布局和延迟元件的插入来实现时钟平衡。 时钟树还从系统时钟信号中得到PCI接口元件的时钟信号。 向PCI接口提供该时钟信号的时钟树部分相对于时钟树的其余部分不平衡。 相反，时钟树的这部分被调节为提供最小的延迟，以便符合PCI总线的定时要求，例如与该时钟信号中的转换相关联的数据建立和保持时间。 因此，时钟树的部分是平衡的，而时钟树的至少一部分不平衡。

公开(公告)号：US06718415B1

公开(公告)日：2004-04-06

申请号：US09569758

申请日：2000-05-12

Applicant: William W. Y. Chu

Inventor： William W. Y. Chu

IPC: G06F110

CPC classification number: G06F13/4282 ,  G06F1/08 ,  G06F1/12 ,  G06F1/1632 ,  G06F13/102 ,  G06F13/20 ,  G06F13/385 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/409 ,  G06F13/42 ,  G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract translation: 用于多处理目的的计算机系统。 计算机系统具有包括第一耦合位置和第二耦合位置的控制台。 每个耦合部位包括连接器。 控制台是能够容纳每个耦合位置的外壳。 该系统还具有多个计算机模块，其中每个计算机模块耦合到连接器。 每个计算机模块具有处理单元，耦合到处理单元的主存储器，耦合到处理单元的图形控制器和耦合到处理单元的大容量存储设备。 每个计算机模块在设计上彼此基本相似，以提供计算机系统中每个计算机模块的独立处理。

公开(公告)号：US06326812B1

公开(公告)日：2001-12-04

申请号：US09625439

申请日：2000-07-26

Applicant: David Jefferson

Inventor： David Jefferson

IPC: G06F110

CPC classification number: G06F1/10 ,  H03K5/13 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/18

Abstract: An integrated circuit programmable logic device comprising: a plurality of programmable logic elements that are responsive to clock signals; a clock signal generation circuit which produces a first clock signal; a first phase shifting element which produces a second clock signal which is a phase-shifted version of the first clock signal, shifted in phase by an amount which compensates for a logic signal delay; and a clock signal distribution network which distributes the first and second clock signals among the programmable logic elements.

Abstract translation: 一种集成电路可编程逻辑器件，包括：响应于时钟信号的多个可编程逻辑元件; 产生第一时钟信号的时钟信号发生电路; 第一相移元件，其产生第二时钟信号，该第二时钟信号是第一时钟信号的相移版本，相位移位补偿逻辑信号延迟的量; 以及在可编程逻辑元件之间分配第一和第二时钟信号的时钟信号分配网络。

公开(公告)号：US06321342B1

公开(公告)日：2001-11-20

申请号：US09274566

申请日：1999-03-23

Applicant: Brian A. Day ,  Timothy E. Hoglund

Inventor： Brian A. Day ,  Timothy E. Hoglund

IPC: G06F110

CPC classification number: G06F1/08

Abstract: A method of interfacing a third circuit with a first circuit that operates based upon a first clock signal and a second circuit that operates based upon a second clock signal includes the step of applying the first clock signal and the second clock signal to a clock selector for the third circuit. The method further includes the step of transferring first data signals between the third circuit and the first circuit at a first rate based upon the first clock signal. Another step of the method includes causing the clock selector to apply the first clock signal to the third circuit prior to the step of transferring the first data signals between the third circuit and the first circuit. Yet another step of the method includes transferring second data signals between the third circuit and the second circuit at a second rate based upon the second clock signal. Furthermore, the method includes causing the clock selector to apply the second clock signal to the third circuit prior to the step of transferring the second data signals between the third circuit and the second circuit. Various apparatus for implementing the method are also disclosed.

Abstract translation: 将第三电路与基于第一时钟信号操作的第一电路和基于第二时钟信号操作的第二电路接口的方法包括将第一时钟信号和第二时钟信号施加到时钟选择器的步骤 第三回路。 该方法还包括基于第一时钟信号以第一速率在第三电路和第一电路之间传送第一数据信号的步骤。 该方法的另一步骤包括使得时钟选择器在第三电路和第一电路之间传送第一数据信号的步骤之前将第一时钟信号施加到第三电路。 该方法的另一步骤包括基于第二时钟信号以第二速率在第三电路和第二电路之间传送第二数据信号。 此外，该方法包括使得时钟选择器在第三电路和第二电路之间传送第二数据信号的步骤之前将第二时钟信号施加到第三电路。 还公开了用于实现该方法的各种装置。

公开(公告)号：US06734718B1

公开(公告)日：2004-05-11

申请号：US10328686

申请日：2002-12-23

Applicant: Feng Pan

Inventor： Feng Pan

IPC: G06F110

CPC classification number: G11C5/145 ,  G11C16/30 ,  H02M3/073 ,  H02M2001/0032 ,  Y02B70/16

Abstract: In a non-volatile memory, charge pumps are used to provide high voltages needed for programming memory cells that have floating gate structures. Charge pumps have a series of voltage multiplier stages in series to boost voltage. These charge pumps must rapidly charge a load to a high voltage and then maintain a voltage with a high degree of stability. Techniques for achieving both of these goals are presented. In one aspect, a charge pump has two operating states, one to charge a load rapidly and a second to maintain a voltage on a charged load with high stability. These states are achieved by changing the current output from a high current during charging to a low current to maintain the voltage. This is done by changing the capacitance used in the individual voltage multiplier stages. In another aspect, two different current levels are produced by changing the voltage used to charge the capacitors of the voltage multiplier stages.

Abstract translation: 在非易失性存储器中，电荷泵用于提供编程具有浮动栅极结构的存储器单元所需的高电压。 电荷泵具有串联的一系列电压倍增器级以提高电压。 这些电荷泵必须快速将负载充电到高电压，然后保持高度稳定的电压。 介绍了实现这两个目标的技术。 在一个方面，电荷泵具有两种操作状态，一种用于快速充电负载，另一种用于以高稳定性来保持充电负载上的电压。 这些状态通过将充电期间的高电流的电流输出改变为低电流来实现，以维持电压。 这是通过改变单个电压倍增器级中使用的电容来实现的。 在另一方面，通过改变用于对电压倍增器级的电容器充电的电压来产生两个不同的电流电平。

公开(公告)号：US06678770B1

公开(公告)日：2004-01-13

申请号：US09579173

申请日：2000-05-25

Applicant: Hideo Sutoh

Inventor： Hideo Sutoh

IPC: G06F110

CPC classification number: G06F13/362

Abstract: In a peripheral component interconnect (PCI) bus system in which both intelligent and non-intelligent devices are connected to the PCI bus, each non-intelligent device is owned and managed by an intelligent device. The intelligent device owning a non-intelligent device provides access to the service functions of the non-intelligent device, making these service functions available even to other devices not possessing device drivers for the non-intelligent device. Accordingly, the PCI bus master does not have to access all devices connected to the PCI bus.

Abstract translation: 在其中智能和非智能设备都连接到PCI总线的外围组件互连（PCI）总线系统中，每个非智能设备都由智能设备拥有和管理。 具有非智能设备的智能设备提供对非智能设备的服务功能的访问，使得即使对于不具有用于非智能设备的设备驱动器的其他设备也可以使用这些服务功能。 因此，PCI总线主机不必访问连接到PCI总线的所有设备。

公开(公告)号：US06185694B2

公开(公告)日：2001-02-06

申请号：US09222957

申请日：1998-12-30

Applicant: Gregory M. Daughtry

Inventor： Gregory M. Daughtry

IPC: G06F110

CPC classification number: G09G5/18 ,  G06F1/10 ,  G06F3/14 ,  G09G5/363

Abstract: A system including a first graphics controller and an expansion slot for coupling a second graphics controller. The first graphics controller generates first graphic symbols based on data stored in the system memory in synchronism with clock signals received from a clock circuit. Similarly, the second graphics controller generates second graphic symbols based on data stored in the system memory in synchronism with clock signals received from the clock circuit. When the second graphics controller is not coupled to the expansion slot, the processor provides a graphics select signal. A clock steering circuit responds to the graphics select signal by applying the clock signals to the first graphics controller, while blocking the clock signals to the expansion slot. In the absence of the graphics select signal, the clock steering circuit applies the clock signals to the expansion slot for application to the second graphics controller, while blocking the clock signals to the first graphics controller.

Abstract translation: 一种包括第一图形控制器和用于耦合第二图形控制器的扩展槽的系统。 第一图形控制器基于从时钟电路接收的时钟信号同步地基于存储在系统存储器中的数据产生第一图形符号。 类似地，第二图形控制器基于从时钟电路接收的时钟信号同步地基于存储在系统存储器中的数据产生第二图形符号。 当第二图形控制器未耦合到扩展槽时，处理器提供图形选择信号。 时钟转向电路通过将时钟信号施加到第一图形控制器，同时将时钟信号阻塞到扩展槽来响应图形选择信号。 在没有图形选择信号的情况下，时钟转向电路将时钟信号施加到扩展槽以应用于第二图形控制器，同时将时钟信号阻挡到第一图形控制器。

公开(公告)号：US06819165B2

公开(公告)日：2004-11-16

申请号：US10435861

申请日：2003-05-12

Applicant: Stacy Ho ,  Thomas James Barber, Jr.

Inventor： Stacy Ho ,  Thomas James Barber, Jr.

IPC: G06F110

CPC classification number: G05F3/262 ,  G05F1/575 ,  H02M3/1584 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16

Abstract: A voltage regulator with dynamically boosted bias current includes a pass device for providing current to a load; an error circuit responsive to a difference between a predetermined reference voltage and a function of the voltage on the load to produce an error signal, a driver circuit responsive to the error signal for controlling the pass device to adjust the current to the load to reduce the error signal, the driver circuit including an amplifier responsive to the error signal for controlling the pass device, a bias current source for biasing the amplifier, a sensing circuit for sensing a portion of the error signal, a reference current source for providing a reference current, a second error circuit responsive to a difference between the portion of the error signal and the reference current to produce a second error current; and a boost circuit responsive to the second error signal to increase the bias current provided to the amplifier when the load demands more current.

Abstract translation: 具有动态升压偏置电流的电压调节器包括用于向负载提供电流的通过装置; 响应于预定参考电压和负载上的电压的函数之间的差异产生误差信号的误差电路，响应于误差信号的驱动器电路，用于控制通过装置以调节到负载的电流以减少 误差信号，所述驱动电路包括响应于用于控制通过装置的误差信号的放大器，用于偏置放大器的偏置电流源，用于感测误差信号的一部分的感测电路，用于提供参考电流的参考电流源 响应于所述误差信号的所述部分与所述参考电流之间的差异产生第二误差电流的第二误差电路; 以及响应于第二误差信号的升压电路，以在负载需要更多电流时增加提供给放大器的偏置电流。