公开(公告)号：US20150181718A1

公开(公告)日：2015-06-25

申请号：US14161122

申请日：2014-01-22

申请人： LUXSHARE-ICT CO., LTD.

发明人： Devin WANG

IPC分类号： H05K3/10 ,  H05K3/22 ,  H05K3/14 ,  H05K3/18 ,  B23K26/36 ,  B23K26/00

CPC分类号： H05K3/188 ,  B23K26/361 ,  B23K26/362 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/50 ,  H05K3/061 ,  H05K3/143 ,  H05K3/146 ,  H05K2201/09018 ,  Y10T29/49155

摘要： A method of forming conductive traces on insulated substrate includes the steps of providing an insulated substrate; forming a coating layer on a surface of the insulated substrate, dividing the coating layer into traces-forming zones and non-traces-forming zones through laser engraving, and removing areas of the coating layer that are located in the traces-forming zones through laser-vaporizing to expose corresponding portions of the surface of the insulated substrate; forming a metallized layer of conductive traces by performing a metallizing treatment on the exposed portions of the insulated substrate and on the coating layer; and directly stripping off the residual coating layer from the non-traces-forming zones or removing it using an acid, an alkaline or a neutral solution.

摘要翻译： 在绝缘基板上形成导电迹线的方法包括提供绝缘基板的步骤; 在绝缘基板的表面上形成涂层，通过激光雕刻将涂层分成痕迹形成区和非痕迹形成区，通过激光去除位于痕迹形成区中的涂层的区域 - 蒸发以暴露绝缘基板的表面的相应部分; 通过对所述绝缘基板的暴露部分和所述涂层进行金属化处理来形成导电迹线的金属化层; 并直接从非痕量形成区剥离残留的涂层，或者使用酸，碱或中性溶液除去残留的涂层。

公开(公告)号：US08435373B2

公开(公告)日：2013-05-07

申请号：US11471223

申请日：2006-06-20

申请人： W. Dennis Slafer

发明人： W. Dennis Slafer

IPC分类号： B32B37/00

CPC分类号： B05D1/28 ,  B05D1/286 ,  B05D1/32 ,  B05D1/322 ,  B05D1/40 ,  B05D3/0263 ,  B05D3/067 ,  B05D3/068 ,  B05D3/141 ,  B05D2252/02 ,  B29C59/046 ,  B29C2035/0827 ,  C23C18/1603 ,  C25D5/022 ,  H01L27/1292 ,  H05K1/0393 ,  H05K3/0079 ,  H05K3/061 ,  H05K3/108 ,  H05K3/143 ,  H05K2203/0113 ,  H05K2203/0143 ,  H05K2203/0264 ,  H05K2203/1545 ,  Y10T156/1023 ,  Y10T156/1039

摘要： Systems and methods are disclosed by which patterns of various materials can be formed on flexible substrates by a continuous roll-to-roll manufacturing process. The patterns may include metallic, transparent conductive, or non-metallic elements with lateral dimensions including in the range from below 100 nanometers to millimeters and with thickness dimensions including the range from tens of Angstroms to greater than 10,000 Angstroms. The substrate may be any material capable of sufficient flexibility for compatibility with roll-based processing equipment, including polymeric films, metallic foils, and thin glass, with polymeric films representing a particularly broad field of application. Methods may include the continuous roll-to-roll formation of a temporary polymeric structure with selected areas open to the underlying substrate, the continuous addition or subtraction of constituent materials, and the continuous removal, where necessary, of the polymeric structure and any excess material.

摘要翻译： 公开了通过连续的卷对卷制造方法可以在柔性基板上形成各种材料的图案的系统和方法。 图案可以包括具有横向尺寸的金属，透明导电或非金属元件，其包括在低于100纳米至毫米的范围内，并且厚度尺寸包括从几十埃到大于10,000埃的范围。 衬底可以是能够具有足够柔性的任何材料，以便与基于辊的加工设备（包括聚合物膜，金属箔和薄玻璃）相容，其中聚合物膜代表特别广泛的应用领域。 方法可以包括连续的卷对卷形成临时聚合物结构，其中选定的区域通向下面的基底，构成材料的连续添加或减少，以及必要时连续除去聚合物结构和任何多余材料 。

公开(公告)号：US08198198B2

公开(公告)日：2012-06-12

申请号：US12458834

申请日：2009-07-23

申请人： Won Hee Yoo ,  Byeung Gyu Chang ,  Yong Suk Kim

发明人： Won Hee Yoo ,  Byeung Gyu Chang ,  Yong Suk Kim

IPC分类号： H01L21/302

CPC分类号： G01R3/00 ,  G01R1/06761 ,  H05K1/0306 ,  H05K3/108 ,  H05K3/143 ,  H05K3/388

摘要： The present invention relates to a method for forming electrode patterns of a ceramic substrate including the steps of: forming a plurality of conductive adhesion patterns on the ceramic substrate to be separated apart from one another; forming a plating seed layer, covering the conductive adhesion patterns, on the ceramic substrate; forming photoresist patterns, exposing parts corresponding to the conductive adhesion patterns, on the plating seed layer; forming a plating layer on the plating seed layer exposed by the photoresist patterns; removing the photoresist patterns; and etching parts of the plating seed layer exposed by removal of the photoresist patterns.

摘要翻译： 本发明涉及一种形成陶瓷基板的电极图案的方法，包括以下步骤：在陶瓷基板上形成多个导电粘合图案以彼此分开; 在陶瓷基板上形成覆盖导电粘合图案的电镀种子层; 在电镀种子层上形成光致抗蚀剂图案，暴露与导电粘合图案相对应的部分; 在由光致抗蚀剂图案曝光的电镀种子层上形成镀层; 去除光致抗蚀剂图案; 以及通过去除光致抗蚀剂图案来蚀刻暴露的电镀种子层的部分。

公开(公告)号：US20110120757A1

公开(公告)日：2011-05-26

申请号：US12622496

申请日：2009-11-20

申请人： David H. Levy

发明人： David H. Levy

IPC分类号： H05K1/02 ,  C23C16/44 ,  C23C16/06 ,  H01L31/0216

CPC分类号： H05K3/143 ,  C23C16/042 ,  C23C16/407 ,  C23C16/45553 ,  H05K2203/1338

摘要： A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is has in its backbone, side chains, or both backbone and side chains, multiple secondary or tertiary amide groups that are represented by the following acetamide structure: >N—C(═O)—. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.

摘要翻译： 用于形成图案化薄膜的诸如原子层沉积方法的化学气相沉积方法包括将沉积抑制剂材料施加到基底上。 沉积抑制剂材料是在其主链，侧链或主链和侧链上具有多个仲或叔酰胺基团的亲水性聚合物，其由以下乙酰胺结构表示：> N-C（= O） - 。 沉积抑制剂材料被图案化同时或随后被应用于基底，以提供有效地不具有沉积抑制剂材料的基底的选定区域。 薄膜仅基本沉积在不具有沉积抑制剂材料的基底的选定区域中。

公开(公告)号：US07657999B2

公开(公告)日：2010-02-09

申请号：US11868640

申请日：2007-10-08

申请人： Thomas Peter Brody

发明人： Thomas Peter Brody

IPC分类号： H05K3/10

CPC分类号： H05K3/28 ,  H05K3/143 ,  H05K3/4647 ,  H05K3/467 ,  H05K2201/09881 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

摘要： In a method of forming an electrical circuit assembly, a substrate is provided including a plurality of first segments that form an electrical circuit. The first segments have surfaces that rise above surfaces of other segments that form the electrical circuit. All of the segments are deposited on the substrate via one or more shadow mask vapor deposition processes in a vacuum. A photoresist caused to cover all of the segments is hardened and then abraded until surfaces of the first segments are exposed, but surfaces of the other segments are not exposed, and a surface of the abraded photoresist is at the same level as the exposed surfaces of the first segments. Second segments can be deposited on the exposed surfaces of the first segments via a shadow mask vapor deposition process in a vacuum to a level above the top surface of the abraded photoresist.

摘要翻译： 在形成电路组件的方法中，提供了包括形成电路的多个第一段的衬底。 第一段具有在形成电路的其他段的表面上方的表面。 所有的片段通过真空中的一个或多个荫罩气相沉积工艺沉积在衬底上。 导致覆盖所有片段的光致抗蚀剂被硬化，然后磨损直到第一片段的表面露出，但是其它片段的表面不被暴露，并且磨损的光致抗蚀剂的表面处于与暴露的表面相同的水平 第一段。 第二段可以通过在真空中的荫罩气相沉积工艺在第一段的暴露表面上沉积到磨损光致抗蚀剂的顶表面上方的水平。

公开(公告)号：US20100003768A1

公开(公告)日：2010-01-07

申请号：US12495724

申请日：2009-06-30

申请人： Michael S. BARNES ,  Terry BLUCK

发明人： Michael S. BARNES ,  Terry BLUCK

IPC分类号： H01L21/308 ,  C23C14/34 ,  C23F4/00 ,  C23F1/08 ,  C23C14/50 ,  H01L21/3065

CPC分类号： H01L21/67173 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/67346 ,  H01L21/67712 ,  H01L31/18 ,  H05K3/143

摘要： Apparatus and methods are provided that enable processing of patterned layers on substrates using a detachable mask. Unlike prior art where the mask is formed directly over the substrate, according to aspects of the invention the mask is made independently of the substrate. During use, the mask is positioned in close proximity or in contact with the substrate so as to expose only portions of the substrate to processing, e.g., sputtering or etch. Once the processing is completed, the mask is moved away from the substrate and may be used for another substrate. The substrate may be cycled for a given number of substrates and then be removed for cleaning or disposal.

摘要翻译： 提供了使用可拆卸掩模在基板上处理图案化层的装置和方法。 与掩模直接形成在衬底上的现有技术不同，根据本发明的方面，掩模独立于衬底制成。 在使用期间，掩模位于与衬底紧密接近或接触的位置，以便只暴露衬底的一部分以进行处理，例如溅射或蚀刻。 一旦处理完成，掩模就从衬底移开并可用于另一衬底。 衬底可以循环给定数量的衬底，然后被移除以进行清洁或处置。

公开(公告)号：US20050067679A1

公开(公告)日：2005-03-31

申请号：US10670975

申请日：2003-09-25

申请人： Kum Leong ,  C. Chung ,  Kian Sim

发明人： Kum Leong ,  C. Chung ,  Kian Sim

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/14 ,  H05K3/38 ,  H05K3/42 ,  H01L21/44 ,  H01L23/02 ,  H01L29/40

CPC分类号： H05K3/421 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/143 ,  H05K3/388 ,  H05K2203/107 ,  H05K2203/1105 ,  H01L2924/00

摘要： A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material. The integrated circuit packaging substrate also includes a via for interconnecting the first layer of conductive material and the second layer of conductive material having a base that includes an interfacial adhesion material to stitch the base of the via to a layer of circuitry.

摘要翻译： 在集成电路封装基板中形成通孔的方法包括在通孔的底部嵌入界面粘合层，并加热通孔底部的材料。 嵌入界面粘合层还包括将导电材料放置在界面粘附层上。 界面层材料沉积在开口的底部，导电材料放置在界面材料的上方。 界面层材料是在通过在通孔开口的基部加热材料产生的温度下扩散到导电材料中的材料。 在通孔开口的底部加热材料包括从开口底部的激光器引导能量。 集成电路封装基板包括第一导电材料层和第二导电材料层。 集成电路封装基板还包括通孔，用于互连第一导电材料层和第二导电材料层，该第二导电材料层具有基底，该基底包括界面粘合材料，以将通孔的基底缝合到电路层。

公开(公告)号：US20040123799A1

公开(公告)日：2004-07-01

申请号：US10334956

申请日：2002-12-31

申请人： Eastman Kodak Company

发明人： Thomas K. Clark

IPC分类号： B05C011/11

CPC分类号： C23C14/12 ,  C23C14/042 ,  H01L51/0011 ,  H05K3/143

摘要： A method of mounting a deposition mask onto a flexible frame for use in vacuum deposition of material through a pealable deposition mask in forming an OLED, including the steps of providing a plate with the pealable deposition mask formed thereon; providing the flexible frame having border portions, such border portions defining a frame opening which corresponds to border portions on the pealable deposition mask; aligning and then securing the border portions of the flexible frame to the border portions of the pealable deposition mask and removing the flexible frame and secured pealable deposition mask from the plate; and mounting the flexible frame with the pealable deposition mask in a carrier which maintains planarity of the pealable deposition mask during subsequent vacuum deposition of material.

摘要翻译： 一种将沉积掩模安装到柔性框架上的方法，用于在形成OLED时通过可分散沉积掩模真空沉积材料，包括以下步骤：在其上形成可喷射沉积掩模; 提供具有边界部分的柔性框架，这种边界部分限定对应于可剥离沉积掩模上的边界部分的框架开口; 对准然后将柔性框架的边界部分固定到可剥离沉积掩模的边界部分，并从该板上移除柔性框架和固定的可分散沉积掩模; 以及将具有可扩散沉积掩模的柔性框架安装在载体中，其在随后的材料真空沉积期间保持可扩散沉积掩模的平面性。

公开(公告)号：US20030196987A1

公开(公告)日：2003-10-23

申请号：US10269770

申请日：2002-10-14

发明人： Moriss Kung ,  Kwun-Yao Ho

IPC分类号： C23F001/00 ,  G11B005/127

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H05K3/143 ,  H05K3/467

摘要： The present invention discloses an ultra fine patterning process for multi-layer substrate by using selective deposition resist which inhibits metal nucleation during metal deposition process. The present invention can be executed by a fine pattern stamp adsorbing the self-assembled monolayers (SAM), then proceeds the stamping process on a surface of a substrate to achieve the selective deposited SAM with ultra fine pattern. Then, the metal deposition process will be proceeded to make metal deposited selectively on the portion not covered by the SAM to form the patterned metal layer directly.

摘要翻译： 本发明公开了一种通过使用在金属沉积工艺中抑制金属成核的选择性沉积抗蚀剂的多层基板的超细图案化工艺。 本发明可以通过吸附自组装单层（SAM）的精细图案印记来执行，然后在基板的表面上进行冲压工艺，以实现具有超细图案的选择性沉积的SAM。 然后，进行金属沉积工艺以使金属选择性地沉积在未被SAM覆盖的部分上以直接形成图案化的金属层。

公开(公告)号：US20010018985A1

公开(公告)日：2001-09-06

申请号：US09798897

申请日：2001-03-06

发明人： Masayuki Kanechika ,  Hideki Urabe ,  Yoshio Kuriyama

IPC分类号： H05K001/03

CPC分类号： H05K1/0242 ,  H05K3/06 ,  H05K3/143 ,  H05K3/146 ,  H05K3/381 ,  H05K3/429 ,  H05K2201/015 ,  H05K2203/092 ,  H05K2203/1152 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A high-frequency circuit board free from variations in transmission impedance and having the desired characteristics is produced. A surface of a resin substrate is activated to form a roughened surface, and a thin-wall pattern of an electrically conductive metal is formed directly on the roughened surface of the resin substrate.

摘要翻译： 产生不具有传输阻抗变化并且具有期望特性的高频电路板。 激活树脂基板的表面以形成粗糙表面，并且直接在树脂基板的粗糙表面上形成导电金属的薄壁图案。