公开(公告)号：US20150381175A1

公开(公告)日：2015-12-31

申请号：US14847285

申请日：2015-09-08

申请人： SK hynix Inc.

发明人： Hyun Woo LEE

IPC分类号： H03K19/00 ,  H03K19/08

CPC分类号： H03K19/0008 ,  H03K3/012 ,  H03K3/356034 ,  H03K19/0013 ,  H03K19/08 ,  H03K19/09436

摘要： A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.

摘要翻译： 半导体装置可以包括模式控制电路，其被配置为响应于掉电模式信号而输出在电流模式逻辑（CML）区域和第一控制信号中摆动的差分输出信号; 第一电路单元，被配置为提供差分输出信号，并以断电模式操作; 以及第二电路单元，被配置为提供差分输出信号，并且在断电模式下在其操作中被中断。

公开(公告)号：US6124734A

公开(公告)日：2000-09-26

申请号：US197486

申请日：1998-11-20

申请人： William H. Davenport

发明人： William H. Davenport

IPC分类号： H03K17/693 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0952 ,  H03K5/12 ,  H03K19/01

CPC分类号： H03K19/01721 ,  H03K19/09436

摘要： A logic circuit output stage includes a first transistor with a first terminal that receives the first logic output signal and a third terminal coupled to a first output node. A second transistor has a first terminal coupled to the first terminal of the first transistor. A third transistor has a first terminal that receives the second logic output signal and a third terminal coupled to a second output node. A fourth transistor has a first terminal coupled to a third terminal of the second transistor and a second terminal coupled to the second output node. An impedance is connected between the third terminal of the second transistor and the first output node. In this output stage, the second transistor provides a transient signal to the first terminal of the fourth transistor in response to a transition in the first logic output signal. The fourth transistor provides a temporary change in the current flowing through the second output node in response to the transient signal received from the second transistor. The temporary current change provided by the fourth transistor allows faster charging or discharging of capacitive loads on the second output node, thereby producing a faster output slew rate. Moreover, the faster output slew rate is produced without significantly increasing either the integrate circuit chip area or the power consumed by the output stage.

摘要翻译： 逻辑电路输出级包括具有接收第一逻辑输出信号的第一端子和耦合到第一输出节点的第三端子的第一晶体管。 第二晶体管具有耦合到第一晶体管的第一端子的第一端子。 第三晶体管具有接收第二逻辑输出信号的第一端子和耦合到第二输出节点的第三端子。 第四晶体管具有耦合到第二晶体管的第三端子的第一端子和耦合到第二输出节点的第二端子。 阻抗连接在第二晶体管的第三端和第一输出节点之间。 在该输出级中，响应于第一逻辑输出信号的转变，第二晶体管向第四晶体管的第一端提供瞬态信号。 响应于从第二晶体管接收的瞬态信号，第四晶体管提供流过第二输出节点的电流的暂时变化。 由第四晶体管提供的临时电流变化允许更快地对第二输出节点上的电容负载进行充电或放电，从而产生更快的输出转换速率。 此外，产生更快的输出转换速率，而不会显着增加集成电路芯片面积或输出级消耗的功率。

公开(公告)号：US5920205A

公开(公告)日：1999-07-06

申请号：US866756

申请日：1997-05-30

申请人： Ebrahim Bushehri ,  Vladimar Bratov ,  Victor I. Staroselski

发明人： Ebrahim Bushehri ,  Vladimar Bratov ,  Victor I. Staroselski

IPC分类号： H03K3/356 ,  H03K17/693 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/21 ,  H03F3/45 ,  H03K19/20

CPC分类号： H03K3/356043 ,  H03K17/693 ,  H03K19/018542 ,  H03K19/09436 ,  H03K19/215

摘要： A loading arrangement for an input stage of a source coupled logic gate comprises a loading element having at least one resistive element and at least one voltage limiting element connected in parallel with one another. There is also disclosed a loading arrangement comprising resistive and voltage limiting elements connected in parallel.

摘要翻译： 用于源耦合逻辑门的输入级的加载装置包括具有至少一个电阻元件的加载元件和彼此并联连接的至少一个限压元件。 还公开了一种负载装置，其包括并联连接的电阻和电压限制元件。

公开(公告)号：US4922135A

公开(公告)日：1990-05-01

申请号：US271124

申请日：1988-11-14

申请人： Pierre Mollier ,  Pascal Tannhof

发明人： Pierre Mollier ,  Pascal Tannhof

IPC分类号： H01L27/095 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0952

CPC分类号： H03K19/09436 ,  H03K19/01721

摘要： The present invention relates to a family of new GaAs MESFET logic circuits including push pull output buffers, which exhibits very strong output driving capability and very low power consumption at fast switching speeds. A 3 way OR/NOR circuit of this invention includes a standard differential amplifier, the first branch of which is controlled by logic input signals. The second branch includes a current switch controlled by a reference voltage. The differential amplifier provides first and second output signals simultaneously and complementary each other. The circuit further includes two push pull output buffers. The first output buffer comprises an active pull up device connected in series with an active pull down device, and the first circuit output signal is available at their common node or at the output terminal. The active pull up device is controlled by a first output signal of the differential amplifier, and the active pull down device is preferably controlled by the second output signal through an intermediate source follower buffer. The second output buffer is of similar structure. The depicted circuit is of the dual phase type. However, if only one phase of the circuit output signal is needed, the output buffer and the intermediate buffer can be eliminated. The number of devices can be even further reduced by eliminating the other remaining intermediate buffer.

公开(公告)号：US4661725A

公开(公告)日：1987-04-28

申请号：US699108

申请日：1985-02-07

申请人： Bernard Chantepie

发明人： Bernard Chantepie

IPC分类号： H01L27/095 ,  H01L21/338 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/812 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0952 ,  H03K19/003 ,  H03K3/356 ,  H03K19/01

CPC分类号： H03K19/09436 ,  H03K19/018542

摘要： An elementary logic circuit obtained by means of Schottky barrier field effect transistors of gallium arsenide includes a differential amplifier, whose first branch, controlled by the input signal E, supplies an output signal S.sub.1, and whose second branch, controlled by a reference signal, supplies an output signal S.sub.2. This circuit further includes two paired level translator stages, the first of which supplies output signal S and the second of which supplies a complementary signal S, the output signal S constituting the reference signal which controls the second branch of the differential amplifier. The circuit can advantageously be used in high-speed IC modules having a lower power consumption, consisting of gallium arsenide and compatible with the circuits realized according to the ECL 100 K technology on silicon.

摘要翻译： 通过砷化镓的肖特基势垒场效应晶体管获得的基本逻辑电路包括差分放大器，其第一分支由输入信号E控制，提供输出信号S1，其第二分支由参考信号控制， 输出信号S2。 该电路还包括两个成对电平转换器级，其中第一级提供输出信号S，第二级提供输出信号S，第二级提供互补信号和上升沿和下降沿S，构成控制差分放大器第二分支的参考信号的输出信号S. 该电路可有利地用于具有较低功耗的高速IC模块，其由砷化镓构成，并且与根据硅上的ECL 100K技术实现的电路兼容。

公开(公告)号：US20100134145A1

公开(公告)日：2010-06-03

申请号：US12327786

申请日：2008-12-03

申请人： Dan P. Bernard ,  John C. Schiff ,  Glen A. Wiedemeier

发明人： Dan P. Bernard ,  John C. Schiff ,  Glen A. Wiedemeier

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528 ,  H03K19/09436

摘要： A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.

摘要翻译： 系统包括被配置为接收第一CML逻辑系列的第一偏置信号和第一CML信号的第一CML缓冲器。 第一CML缓冲器基于第一CML信号和第一偏置信号产生第一CML逻辑系列的第二CML信号。 第一耦合电容器模块耦合到第一CML缓冲器。 第一耦合电容器模块接收第二CML信号并且基于第二CML信号产生第三CML信号。 第二CML缓冲器耦合到耦合电容器模块并且接收第二偏置信号和第三CML信号，产生第二CML逻辑系列的第四CML信号。 反馈模块耦合到第二CML缓冲器并且接收产生第五CML信号的第四CML信号。 第二CML缓冲器基于第二偏置信号，第三CML信号和第五CML信号产生第四CML信号。

公开(公告)号：US06774721B1

公开(公告)日：2004-08-10

申请号：US10406360

申请日：2003-04-04

申请人： Petre Popescu ,  Junxian Weng ,  David Alexander Brinton Dobson ,  Guy Jacque Joseph Fortier

发明人： Petre Popescu ,  Junxian Weng ,  David Alexander Brinton Dobson ,  Guy Jacque Joseph Fortier

IPC分类号： H03F345

CPC分类号： H03K5/003 ,  H03K19/018514 ,  H03K19/09436 ,  H03M9/00

摘要： Quake Transistor Logic (QTL) circuits of the embodiments of the invention are low power, high-speed circuits that can be manufactured by the same process as the lower-speed complex circuits, and are thus capable of being integrated on the same device. A number of techniques are employed to give QTL circuits their unique advantages. Lower power without loss of speed is achieved through the use of a self-biasing clock buffer to eliminate the need for tail current sources in the logic; differential signals are employed throughout to improve noise immunity with a low logic signal swing; an optional tuning circuit provides extension of the frequency response to achieve an even higher clock frequency and logic circuit bandwidth.

摘要翻译： 本发明实施例的地震晶体管逻辑（QTL）电路是能够通过与低速复合电路相同的处理制造的低功率，高速电路，因此能够集成在同一设备上。 采用多种技术为QTL电路提供独特的优势。 通过使用自偏置时钟缓冲器来消除对逻辑中的尾部电流源的需要来实现低功率而不损失速度。 整个采用差分信号，通过低逻辑信号摆幅提高噪声抗扰度; 可选的调谐电路提供频率响应的扩展，以实现更高的时钟频率和逻辑电路带宽。

公开(公告)号：US5289057A

公开(公告)日：1994-02-22

申请号：US42

申请日：1993-01-04

申请人： Yasushi Kinugasa

发明人： Yasushi Kinugasa

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K19/0952 ,  H03K19/092

CPC分类号： H03K19/09436

摘要： A level shift circuit composed of two terminals which are different in potential level, at least two capacitors each incorporating a ferroelectric material and connected to each other in series between the two terminals, and output terminals each provided on one side of each of the capacitors, so that the output terminals are capable of outputting respective signals which are different in direct-current voltage level.

摘要翻译： 由电位电平不同的两个端子组成的电平移动电路，至少两个电容器，每个电容器都包含铁电材料并且彼此串联连接在两个端子之间;以及输出端子，每个电容器设置在每个电容器的一侧， 使得输出端子能够输出直流电压电平不同的各个信号。

公开(公告)号：US4928024A

公开(公告)日：1990-05-22

申请号：US344405

申请日：1989-04-28

申请人： Isao Shimotsuhama ,  Shinji Emori ,  Yoshio Watanabe ,  Masaya Tamamura

发明人： Isao Shimotsuhama ,  Shinji Emori ,  Yoshio Watanabe ,  Masaya Tamamura

IPC分类号： H03K19/086 ,  H03K19/094

CPC分类号： H03K19/086 ,  H03K19/09436

摘要： An ECL transistor pair is connected in parallel with a third transistor. A complementary signal is applied to the transistor pair. A high level of a signal that is applied to the third transistor is effectively higher than a high level of the input to the pair of transistors; and a low level of the signal applied to the third transistor is effectively lower than the high level of the input to the pair of transistors. The low level input to the third transistor enables the ECL circuit to output the complementary input signal and assures high speed ECL operation. The high level of the input to the third transistor disables the ECL circuit from outputting the complementary input signal.

公开(公告)号：US4780687A

公开(公告)日：1988-10-25

申请号：US57560

申请日：1987-06-03

申请人： Thierry Ducourant

发明人： Thierry Ducourant

IPC分类号： H03K19/0185 ,  G11C11/419 ,  H03F3/45 ,  H03K19/094

CPC分类号： H03F3/45376 ,  H03K19/09436

摘要： A differential amplifier circuit for regenerating complementary analog signals of low amplitude includes a differential pair of field effect transistors whose common sources are connected to a first supply voltage V.sub.SS via a load, a pair of loads which are connected to the drain of each transistor of the differential pair and to a second supply voltage, respectively, and a level regenerating circuit having a pair of diodes for deriving the signals from the drain of each transistor of the differential pair. The signals transported by the diodes are applied to the lower transistor of a pair of push-pull stages whose upper transistor directly receives the signal derived from the drain of the other transistor of the differential pair, while the source of the lower transistors of the push-pull stages is connected to ground and the drain of the upper transistor of these stages is connected to the second supply voltage V.sub.DD, the complementary amplified output signals being available at the central points of the push-pull stages.

摘要翻译： 用于再生低幅度的互补模拟信号的差分放大器电路包括一个场效应晶体管的差分对，其公共源经由负载连接到第一电源电压VSS，一对负载连接到每个晶体管的漏极 差分对和第二电源电压，以及具有用于从差分对的每个晶体管的漏极导出信号的一对二极管的电平再生电路。 由二极管传送的信号被施加到一对推挽级的下晶体管，其上级晶体管直接接收从差分对的另一晶体管的漏极导出的信号，而推挽级的下晶体管的源 - 级级连接到地，并且这些级的上级晶体管的漏极连接到第二电源电压VDD，互补放大的输出信号在推挽级的中心点可用。