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公开(公告)号：US20080137250A1
公开(公告)日：2008-06-12
申请号：US11567794
申请日：2006-12-07
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： A protection circuit with a positive field effect transistor coupled to a power source, a negative field effect transistor connected to a pass-gate and a circuit ground, a circuit input terminal, a multi-level source of protection voltage coupled to an external circuit and at least three additional field effect transistors. A drain of the negative field effect transistor couples to a gate of the positive field effect transistor. When the circuit input terminal is low the pass-gate is on; when the circuit input terminal is high the pass-gate is off. Embodiments of the invention also include stacks of three or more field effect transistors.
摘要翻译： 具有耦合到电源的正场效应晶体管的保护电路，连接到通过栅极和电路接地的负场效应晶体管，电路输入端子，耦合到外部电路的多电平保护电压源，以及 至少三个附加场效应晶体管。 负场效应晶体管的漏极耦合到正场效应晶体管的栅极。 当电路输入端子为低电平时，通路导通; 当电路输入端子为高电平时，通电门断开。 本发明的实施例还包括三个或更多个场效应晶体管的堆叠。
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2.发明授权公开(公告)号：US07821300B2
公开(公告)日：2010-10-26
申请号：US12327786
申请日：2008-12-03
IPC分类号： H03K19/086 , H03B1/00
CPC分类号： H03K19/018528 , H03K19/09436
摘要： A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.
摘要翻译： 系统包括被配置为接收第一CML逻辑系列的第一偏置信号和第一CML信号的第一CML缓冲器。 第一CML缓冲器基于第一CML信号和第一偏置信号产生第一CML逻辑系列的第二CML信号。 第一耦合电容器模块耦合到第一CML缓冲器。 第一耦合电容器模块接收第二CML信号并且基于第二CML信号产生第三CML信号。 第二CML缓冲器耦合到耦合电容器模块并且接收第二偏置信号和第三CML信号，产生第二CML逻辑系列的第四CML信号。 反馈模块耦合到第二CML缓冲器并且接收产生第五CML信号的第四CML信号。 第二CML缓冲器基于第二偏置信号，第三CML信号和第五CML信号产生第四CML信号。
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公开(公告)号：US20100134145A1
公开(公告)日：2010-06-03
申请号：US12327786
申请日：2008-12-03
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/09436
摘要： A system includes a first CML buffer configured to receive a first bias signal and a first CML signal of a first CML logic family. The first CML buffer produces a second CML signal of the first CML logic family based on the first CML signal and the first bias signal. A first coupling capacitor module couples to the first CML buffer. The first coupling capacitor module receives the second CML signal and produces a third CML signal based on the second CML signal. A second CML buffer couples to the coupling capacitor module and receives a second bias signal and the third CML signal, producing a fourth CML signal of a second CML logic family. A feedback module couples to the second CML buffer and receives the fourth CML signal producing a fifth CML signal. The second CML buffer is produces the fourth CML signal based on the second bias signal, the third CML signal, and the fifth CML signal.
摘要翻译： 系统包括被配置为接收第一CML逻辑系列的第一偏置信号和第一CML信号的第一CML缓冲器。 第一CML缓冲器基于第一CML信号和第一偏置信号产生第一CML逻辑系列的第二CML信号。 第一耦合电容器模块耦合到第一CML缓冲器。 第一耦合电容器模块接收第二CML信号并且基于第二CML信号产生第三CML信号。 第二CML缓冲器耦合到耦合电容器模块并且接收第二偏置信号和第三CML信号，产生第二CML逻辑系列的第四CML信号。 反馈模块耦合到第二CML缓冲器并且接收产生第五CML信号的第四CML信号。 第二CML缓冲器基于第二偏置信号，第三CML信号和第五CML信号产生第四CML信号。
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公开(公告)号：US07457091B2
公开(公告)日：2008-11-25
申请号：US11567794
申请日：2006-12-07
IPC分类号： H02H3/20
CPC分类号： H02H9/046
摘要： A protection circuit with a positive field effect transistor coupled to a power source, a negative field effect transistor connected to a pass-gate and a circuit ground, a circuit input terminal, a multi-level source of protection voltage coupled to an external circuit and at least three additional field effect transistors. A drain of the negative field effect transistor couples to a gate of the positive field effect transistor. When the circuit input terminal is low the pass-gate is on; when the circuit input terminal is high the pass-gate is off. Embodiments of the invention also include stacks of three or more field effect transistors.
摘要翻译： 具有耦合到电源的正场效应晶体管的保护电路，连接到通过栅极和电路接地的负场效应晶体管，电路输入端子，耦合到外部电路的多电平保护电压源，以及 至少三个附加场效应晶体管。 负场效应晶体管的漏极耦合到正场效应晶体管的栅极。 当电路输入端子为低电平时，通路导通; 当电路输入端子为高电平时，通电门断开。 本发明的实施例还包括三个或更多个场效应晶体管的堆叠。
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