摘要:
Methods and apparatus to design collaborative automation systems based on Data Distribution Service middleware are described, which include a clustered automation platform having one or more control servers connected to a local area control network, and a plurality of self-contained process interface systems configured to receive electrical signals from one or more field instruments and forward resulting data via an uplink to a local area input/output network. The clustered automation platform also includes an input/output processing and inferential modeling server connected to the local area input/output network and configured to process input/output signals of the plurality of self-contained process interface systems. The clustered automation platform also includes real-time data distribution service control middleware configured to interconnect one or more process control applications, the one or more input/output processing and inferential modeling servers, the one or more control servers, the plurality of self-contained process interface systems, and one or more HMIs.
摘要:
Memory technologies for storing filter samples include RAMs and CCDs. Adaptive memory capability and memory servo capability improve memory characteristics. In a RAM embodiment, a detector is used to detect a memory address condition and to control the memory and the memory address register in response thereto. In a CCD embodiment, a detector is used to detect a memory reference signal and to refresh the memory signals in response thereto. Improved memory refresh, memory performance, and memory capacity enhance system characteristics. Improved memory architecture provides advantages of increased speed, lower cost, and efficiency of implementation. Information stored in memory can be scanned out at a rate greater than the addressing rate associated with the memories. This permits higher speed operation with lower cost memories. Use of an output buffer, such as a FIFO, permits normalization of memory clock rates.
摘要:
A filter processor provides improved capabilities and reduced complexity by inputting and processing lower resolution signals and by generating higher resolution filtered signals. In a preferred embodiment; an incremental filter processor generates incremental input signals, performs incremental processing, and generates multi-bit filtered signals. Input signals are received from radar, sonar, seismic, or other sources; are processed by the filter processor to generate filtered signals; and can be post processed by a post processor. In a preferred embodiment, the input circuit is a serial input and parallel output circuit, such as a delay line or a CCD; the filter processor is an incremental fast Fourier transform processor; and the post processor is an incremental frequency domain correlator. Other post processors include a frequency domain integrator and an RSS post processor to convert coherent signal samples to noncoherent signal samples.
摘要:
An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contension or conflicts with computer operations and to share control circuitry.
摘要:
An incremental digital filter provides high speed and low cost capability such as for performing fast Fourier transforms (FFTs), correlations, convolutions, and other digital filter operations. One configuration operates at microwave sample rates, computing a complete 512-point FFT in 0.2 microseconds for an effective sample rate of 2.56 gigahertz. High speed and low cost are derived from a parallel pipeline architecture in combination with incremental processing. Parallel pipeline architecture provides extremely high speed while the incremental mechanization provides a simple arrangement with a low component count for low cost. The incremental nature of the processor provides an integrating type mechanization, where integration-after-transformation yields high processing gain for signal-to-noise-ratio enhancement.High data rate input and output mechanizations are provided to accommodate the high processing rates. An improved input mechanization involves analog signal to incremental digital conversion. An improved output mechanization involves integration after filtering for data rate reductions and for signal enhancement and also involves a bus output structure for multiplexing of output parameters.
摘要:
A system is provided for voice signal processing including recognizing input voice messages and generating output voice messages. Digital processing of voice signals yields particular advantages. Voice responsive operations provide operator interaction flexibility. Communication of digital information in response to voice information provides data compression for communication applications. Other applications of the voice signal processing system include an audionic clock, an audionic calculator, and an audionic announciator.