公开(公告)号：US20240186140A1

公开(公告)日：2024-06-06

申请号：US18221976

申请日：2023-07-14

申请人： Shanghai Huali Microelectronics Corporation

发明人： Tao Wang

IPC分类号： H01L21/02

CPC分类号： H01L21/02639 ,  H01L21/02236 ,  H01L21/02255

摘要： The present application discloses a method for forming a mixed substrate. By optimizing the process flow, adding a silicon oxide sidewall process and covering an SOI area sidewall after dry etching with protective silicon oxide, epitaxial silicon growth on the SOI area sidewall is prevented, so that a bulge is prevented from being formed at a boundary between an SOI area and a silicon substrate area when the silicon substrate area is formed on an SOI silicon wafer. At the same time, since STI is eventually formed at the boundary between the SOI area and the silicon substrate area, the actual structure of a device formed on the mixed substrate remains basically unchanged, thus improving the product yield. The method for forming the mixed substrate is particularly suitable for an SOI gate-last process.

公开(公告)号：US20240128976A1

公开(公告)日：2024-04-18

申请号：US18231851

申请日：2023-08-09

申请人： Shanghai Huali Microelectronics Corporation

发明人： Yu Jia ,  Yifei Qian

IPC分类号： H03K19/0185 ,  H03K17/22 ,  H03K17/687

CPC分类号： H03K19/018521 ,  H03K17/223 ,  H03K17/6872

摘要： The present application discloses a power-on-reset circuit, which optimizes a hysteresis circuit and a reset signal generation circuit, and introduces a seventh PMOS transistor as a switch transistor to achieve the differentiation of control voltages at a gate end of a first NMOS transistor during powering-on and off. A voltage rise detection point is determined by a partial voltage of a resistor during powering-on, while a voltage fall detection point is directly determined by a power supply voltage during powering-off. Such differentiation may achieve a significant separation between the voltage rise detection point and the voltage fall detection point, reducing the voltage fall detection point to near a threshold voltage of the first NMOS transistor, and meeting the demand for a lower voltage fall detection point, which is consistent with a practical application of the power-on-reset circuit in an MCU.

公开(公告)号：US11911809B2

公开(公告)日：2024-02-27

申请号：US17958548

申请日：2022-10-03

申请人： Shanghai Huali Microelectronics Corporation

发明人： Minjie Chen ,  Jin Xu ,  Zaifeng Tang ,  Yu Ren

IPC分类号： B08B5/00 ,  H01L21/67 ,  B08B9/08 ,  H01L21/683

CPC分类号： B08B5/00 ,  B08B9/08 ,  H01L21/67069 ,  H01L21/6831 ,  B08B2209/08

摘要： The present application discloses a preventive maintenance method for a chamber of a metal etching machine. An optimized burning cleaning recipe is added before the chamber is opened, and metal substances remaining on the surface of an electrostatic chuck are removed by adopting a cleaning/pumping down multi-step alternate method. Before the chamber is opened for preventive maintenance, the phenomenon of metal particles remaining on the surface of the electrostatic chuck can be significantly improved, thus solving the downtime problem caused by abnormal backside helium and ensuring the stability of mass production.

公开(公告)号：US20230410279A1

公开(公告)日：2023-12-21

申请号：US17941222

申请日：2022-09-09

申请人： Shanghai Huali Microelectronics Corporation

发明人： Junjun Zhuang ,  Xu Chen ,  Yansheng Wang ,  Zhengying Wei

IPC分类号： G06T7/00 ,  G06V10/50

CPC分类号： G06T7/0004 ,  G06V10/50 ,  G06T2207/30148 ,  G06T2207/10052

摘要： The present application provides a method for automatically detecting a wafer backside brightfield image anomaly, at least comprising: processing wafer backside brightfield images by means of histogram equalization, so as to obtain processed images; compiling statistics for a gray histogram of the processed images; calculating the number of abnormal pixels in each of the images; and providing a threshold, and highlighting the image with a score less than the threshold. In the present application, the wafer backside brightfield images are analyzed by means of image preprocessing and a specific calculation method, so as to quickly and automatically detect an abnormal wafer backside image.

公开(公告)号：US11723197B2

公开(公告)日：2023-08-08

申请号：US17409146

申请日：2021-08-23

申请人： Shanghai Huali Microelectronics Corporation

发明人： Lei Zhang ,  Tao Hu ,  Xiaochuan Wang ,  Zhi Tian ,  Qiwei Wang ,  Haoyu Chen

IPC分类号： H10B41/35 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L21/04 ,  H10B41/00 ,  H10B41/27

CPC分类号： H10B41/35 ,  H01L21/046 ,  H01L21/0415 ,  H01L21/265 ,  H01L21/823418 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/00 ,  H10B41/27 ,  H01L29/7881

摘要： The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.

公开(公告)号：US11545482B2

公开(公告)日：2023-01-03

申请号：US17217644

申请日：2021-03-30

申请人： Shanghai Huali Microelectronics Corporation

发明人： Tianzhi Zhu ,  Guanqun Huang ,  Haoyu Chen ,  Hua Shao

IPC分类号： H01L29/87 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8228

摘要： The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type lightly doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type lightly doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

公开(公告)号：US11462627B2

公开(公告)日：2022-10-04

申请号：US17244620

申请日：2021-04-29

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Xiang Peng ,  Haoyu Chen ,  Qiwei Wang

IPC分类号： H01L29/66

摘要： The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.

公开(公告)号：US11315942B2

公开(公告)日：2022-04-26

申请号：US16666418

申请日：2019-10-29

申请人： Shanghai Huali Microelectronics Corporation

发明人： Xiaoliang Tang ,  Guanglong Chen ,  Naoki Tsuji ,  Hua Shao

IPC分类号： H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L27/02 ,  H01L27/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/78 ,  G11C16/04

摘要： The present disclosure provides a SONOS memory structure and a manufacturing method therefor. The SONOS memory structure including a substrate and a select transistor gate and a memory transistor gate formed on the substrate, wherein the substrate is a composite substrate including a base silicon layer, a buried oxide layer and a surface silicon layer, wherein the upper portion of the base silicon layer has a memory transistor well region formed therein; the select transistor gate and the memory transistor gate are formed on the surface silicon layer; the select transistor gate comprises a first select transistor gate and a second select transistor gate, the first select transistor gate and the second select transistor gate are respectively located at two sides of the memory transistor gate, and are electrically isolated from the memory transistor gate by first spacers on both sides of the memory transistor gate.

公开(公告)号：US11302867B2

公开(公告)日：2022-04-12

申请号：US16850993

申请日：2020-04-16

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Youqing Tang ,  Zhigang Zhang

IPC分类号： H01L45/00

摘要： A method for making an RRAM resistive structure includes, step 1, forming a via structure, which includes depositing an ultra-low dielectric constant material layer on a substrate, depositing a copper layer on the ultra-low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer. step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure without dishing; step 3, forming a first TiN layer on the TaN-filled via structure; and step 4, forming an RRAM resistive structure stack having layers of TaOx, Ta2O5, Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure.

公开(公告)号：US20220069145A1

公开(公告)日：2022-03-03

申请号：US17142431

申请日：2021-01-06

申请人： Shanghai Huali Microelectronics Corporation

发明人： Chenchen Qiu ,  Jun Qian ,  Chang Sun ,  Zhengying Wei

IPC分类号： H01L31/0352 ,  H01L27/146 ,  H01L31/18

摘要： The disclosure discloses a method for forming a doped epitaxial layer of contact image sensor. Epitaxial growth is performed in times. After each time of epitaxial growth, trench isolation and ion implantation are performed to form deep and shallow trench isolation running through a large-thickness doped epitaxial layer. Through cyclic operation of epitaxial growth, trench isolation and ion implantation, the photoresist and hard mask required at each time do not need to be too thick. In the process of trench isolation and ion implantation, the photoresist and etching morphologies are good, such that the lag problem of the prepared contact image sensor is improved. By forming the large-thickness doped epitaxial layer by adopting the method for forming the doped epitaxial layer of the contact image sensor, a high-performance contact image sensor applicable to high quantum efficiency, small pixel size and near infrared/infrared can be prepared.