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公开(公告)号：US10536861B2
公开(公告)日：2020-01-14
申请号：US13866751
申请日：2013-04-19
摘要： The stability of a channel in a wireless network is evaluated at a node. Upon transmitting a packet from the node on a network channel, a first counter associated with the channel is incremented. Upon receiving an acknowledgment packet responsive to the transmitted packet, a second counter associated with the channel is incremented. A stability metric for the channel is computed based on values stored in the first and second counters. Additionally, interference on a channel of the network is measured at a node. Upon determining that no packet is received during a predetermined time-period on the channel, a received signal strength (RSS) is measured on the channel at an end of the predetermined time-period. Alternatively, upon determining that a packet is received during the predetermined time-period on the channel, the RSS is measured on the channel following completion of the transmission of the packet on the channel.
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公开(公告)号：US10447152B2
公开(公告)日：2019-10-15
申请号：US15465504
申请日：2017-03-21
发明人： Xu Zhang , Jian Li , San Hwa Chee
摘要： A method and system of driving a switched capacitor converter having a plurality of switches. A first driver coupled to a first switch is powered by providing a first reference voltage level VCC to a first supply and a GND reference to a second supply node of the first driver. A second driver coupled to a second switch is powered by providing a unidirectional path between the first supply node of a first driver and the first supply node of the second driver and by keeping OFF the second switch while turning ON the first switch. A third driver coupled to a third switch is powered by providing a unidirectional path between the first supply node of a second driver and the first supply node of the third driver and by keeping OFF the first and third switch while turning ON the second switch.
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公开(公告)号：US10013003B2
公开(公告)日：2018-07-03
申请号：US13764045
申请日：2013-02-11
发明人： Gregory Manlove , Yi Ding Gu , Jian Li
CPC分类号： G05F1/10 , G05F1/562 , H02M1/32 , H02M3/142 , H02M3/156 , H02M3/158 , H02M2001/0019 , H02M2001/0025
摘要： A switching regulator circuit incorporates an offset circuit, connected in a control loop of the regulator circuit, that, in response to a signal indicating an imminent load current step, adjusts a duty cycle of a power switch for the current step prior to the regulator circuit responding to a change in output voltage due to the current step. In one embodiment, a load controller issues a digital signal shortly before a load current step. The digital signal is decoded and converted to an analog offset signal in a feedback control loop of the regulator to immediately adjust a duty cycle of the switch irrespective of the output voltage level. By proper timing of the offset, output voltage ripple is greatly reduced. The current offset may also be used to rapidly change the output voltage in response to an external signal requesting a voltage step.
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公开(公告)号：US20170345744A1
公开(公告)日：2017-11-30
申请号：US15167345
申请日：2016-05-27
发明人： Edward William Olsen
IPC分类号： H01L23/495 , H01L23/31 , H01L23/00
摘要： A flipchip may include: a silicon die having a circuit side with solder bumps and a non-circuit side; a leadframe attached to the solder bumps on the circuit side of the silicon die; a heat spreader attached to the non-circuit side of the silicon die; and encapsulation material encapsulating the silicon die, a portion of the leadframe, and all but one exterior surface of the heat spreader. The leadframe may have NiPdAu plating on the portion that is not encapsulated by the encapsulation material and no plating on the portion that is attached to the solder bumps.
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公开(公告)号：US09825553B2
公开(公告)日：2017-11-21
申请号：US14531520
申请日：2014-11-03
CPC分类号： H02M7/217 , H02J5/005 , H02J17/00 , H02J50/12 , H02M2001/0058 , Y02B70/1441 , Y02B70/1491
摘要： A control system is provided for controlling a power receiving circuit which is configured for receiving power wirelessly and producing an output voltage. The power receiving circuit has a resonant LC circuit including an inductive element and a capacitive element coupled in parallel. The control system includes a switching circuit coupled in parallel to the resonant LC circuit, and a feedback loop circuit configured for regulating the output voltage by controlling duration during which the switching circuit is in a conductive state in each cycle of a voltage developed across the resonant LC circuit.
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公开(公告)号：US09811113B2
公开(公告)日：2017-11-07
申请号：US15208482
申请日：2016-07-12
摘要： A method synchronizes clock signals generated by a system that includes multiple PLLs that are connected in parallel and output frequency dividers driven by the PLLs. The system receives a common frequency reference signal and a common synchronization signal. Each PLL may have a reference signal frequency divider. The reference frequency divider may be phase-reset, for example, by a transition to a first logic state in the synchronization signal, and the output frequency dividers are each phase-reset, for example, by a transition to a second logic state following the transition to the first logic state in the synchronization signal. The transition to the first logic state may be, for example, a rising edge.
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公开(公告)号：US09793800B1
公开(公告)日：2017-10-17
申请号：US15479162
申请日：2017-04-04
发明人： Yingyi Yan , Yi Ding Gu
CPC分类号： H02M3/157 , H02M1/084 , H02M1/12 , H02M1/14 , H02M3/1584 , H02M2001/0009
摘要： In a multiphase, current mode controlled switching power supply, current through the inductors in the various phases is sensed to determine when to turn off the switching transistors. An AC current feedback path, sensing the ramping ripple current, is separate from the DC current path, sensing the lower frequency average current. A shared differential amplifier has its inputs multiplexed to receive only the DC component signals from all the phases. The gain of the amplifier is set so that the DC sense signal has the proper proportion to the AC sense signal. The output of the amplifier is sampled and held for each phase using a second multiplexer. The AC sense signal and the amplified DC sense signal, for each phase, are combined by a summing circuit. The composite sense signal is applied to a comparator for each phase to control the duty cycle of the associated switch.
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公开(公告)号：US09748843B2
公开(公告)日：2017-08-29
申请号：US14677794
申请日：2015-04-02
发明人： Xu Zhang , Jian Li , Zhouyuan Shi , Yi Ding Gu
CPC分类号： H02M3/1582 , H02M2001/0009
摘要： An inductor current-sensing circuit for measuring a current in an inductor includes (a) a first RC network coupled between a first terminal of the inductor and a reference voltage source; and (b) a second RC network coupled between a second terminal of the inductor and the reference voltage source. The first RC network and the second RC network each have a time constant substantially equal to the ratio between the inductance and the DC resistance of the inductor. The inductor which current is being measured may be a primary inductor of a four-switch buck boost converter receiving an input voltage and providing an output voltage.
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公开(公告)号：US09691681B2
公开(公告)日：2017-06-27
申请号：US15154489
申请日：2016-05-13
发明人： Edward William Olsen
IPC分类号： H01L21/44 , H01L23/367 , H01L23/31 , H01L23/48 , H01L23/433 , H01L23/498 , H01L21/48 , H01L23/538 , H01L23/00 , H01L21/268 , H01L21/285 , H01L21/288 , H01L21/3105 , H01L21/56 , H01L21/768 , H01L23/373 , H01L23/36
CPC分类号： H01L23/3675 , H01L21/268 , H01L21/2855 , H01L21/2885 , H01L21/3105 , H01L21/486 , H01L21/56 , H01L21/76802 , H01L21/76879 , H01L23/3107 , H01L23/36 , H01L23/3736 , H01L23/4334 , H01L23/481 , H01L23/49827 , H01L23/49861 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/83 , H01L2224/04105 , H01L2224/16245 , H01L2224/19 , H01L2224/29111 , H01L2224/2912 , H01L2224/2919 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/83005 , H01L2224/83801 , H01L2224/8385 , H01L2924/01029 , H01L2924/10253 , H01L2924/14
摘要： A method of making an integrated circuit package that contains a semiconductor die having one or more electrical connections to an electronic circuit within the semiconductor die. The method may include: encapsulating the semiconductor die and its electrical connections in non-electrically conductive, encapsulation material; laser drilling the encapsulation material to expose one of the electrical connections within the integrated circuit package, thereby creating a via opening in an external surface of the encapsulation material to the electrical connection; and electroplating or sputtering over the via opening in the encapsulation material to create a conductive routing layer from the exterior surface of the encapsulation material to the electrical connection.
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公开(公告)号：US09685933B2
公开(公告)日：2017-06-20
申请号：US14669863
申请日：2015-03-26
CPC分类号： H03H19/004 , H02M1/15 , H02M3/07 , H03F3/45475
摘要： A notch filter is controlled synchronously with a chopper to filter out chopping ripple. In one embodiment, the notch filter is coupled to the differential output of the chopper and includes a sampling capacitor, a hold capacitor, and a second set of switches between the sampling capacitor and the hold capacitor. The second set of switches is temporarily closed once per chopper switching cycle to transfer charge from the sampling capacitor to the hold capacitor such that the ripple from the chopper is not transferred to the hold capacitor. The voltage across the hold capacitor may be coupled to any other circuit, such as to the differential inputs of an amplifier.
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