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公开(公告)号：US10706177B2
公开(公告)日：2020-07-07
申请号：US15638564
申请日：2017-06-30
发明人： Hiroshi Watanabe , Takeshi Hamamoto
摘要： A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.
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公开(公告)号：US10341122B2
公开(公告)日：2019-07-02
申请号：US15643672
申请日：2017-07-07
申请人： Hiroshi Watanabe
IPC分类号： H04L9/32 , G06F21/73 , G11C16/20 , H04L9/08 , G06F7/58 , G06F21/44 , G06F21/60 , G06F21/70 , G06F21/86 , H01L23/535 , H01L27/108 , H04L12/24 , G11C7/24 , G11C13/00 , G11C16/22 , G11C11/22 , G11C11/16 , H04L29/06 , G11C29/44
摘要： A network of electronic appliances includes a plurality of network units of electronic appliances. The network units include a first network unit and a plurality of second network units. The first network unit is connected to at least one of the second network units. Each of the network units includes a stem server and a plurality of peripheral devices connected to the stem server. The stem server includes at least one passcode and at least one list of a plurality of registration codes. Each list is associated to a respective passcode. Each registration code of one list associating to one passcode corresponds to a respective peripheral device. Each registration code is generated in response to a respective passcode using physical randomness of a respective peripheral device in correspondence to the passcode. An address of each identification cell is defined by several word lines and bit lines.
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公开(公告)号：US4281029A
公开(公告)日：1981-07-28
申请号：US80220
申请日：1979-10-01
IPC分类号： C01G15/00 , B01J12/00 , B01J12/02 , C23C14/06 , C23C14/22 , C23C14/24 , C23C14/32 , C30B23/02 , C30B23/08 , C30B25/06 , H01L21/203 , B05D3/06 , C23C13/08 , H01L7/36
CPC分类号： C23C14/228 , C23C14/221 , C23C14/24 , C23C14/243 , C30B23/02 , C30B23/08 , Y10S148/006 , Y10S148/045 , Y10S148/064 , Y10S148/065 , Y10S148/072 , Y10S148/169 , Y10S438/935 , Y10S438/961 , Y10S438/971
摘要： A method of coating which comprises the steps of separately vaporizing a plurality of substances containing the component elements of a desired compound and placed in a plurality of crucibles to form vapors of the substances, mixing the vapors in a heated mixing chamber to form a mixed vapor, jetting the mixed vapor into a vacuum region to form clusters, ionizing the clusters to form cluster ions, and accelerating the cluster ions to make them impinge on a substrate.An apparatus for coating which comprises a plurality of crucibles for separately vaporizing substances containing the component elements of a desired compound to form vapors of the substances, a mixing chamber for heating and mixing the vapors introduced therein to form a mixed vapor, the mixing chamber having at least one injection hole for jetting the mixed vapor into a vacuum region, communication pipes for connecting the mixing chamber to the crucibles, an ionization chamber for ionizing clusters produced from the mixed vapor jetted from the mixing chamber, means for accelerating cluster ions produced in the ionization chamber and making them impinge on a substrate, and a substrate holder for holding the substrate.
摘要翻译： 一种涂覆方法，其包括以下步骤：将含有所需化合物的组分元素的多种物质分开蒸发并放置在多个坩埚中以形成物质的蒸气，将蒸气混合在加热的混合室中以形成混合蒸气 将混合的蒸汽喷射到真空区域以形成簇，使簇离子形成簇离子，并加速簇离子使其撞击在基底上。 一种用于涂覆的装置，包括用于单独蒸发含有所需化合物的组分元素的物质的坩埚，以形成物质的蒸气;混合室，用于加热和混合引入其中的蒸气以形成混合蒸气，所述混合室具有 用于将混合蒸汽喷射到真空区域中的至少一个喷射孔，用于将混合室连接到坩埚的连通管，用于从由混合室喷射的混合蒸气产生的离子簇的离子化室，用于加速由 电离室并使其撞击在基板上，以及用于保持基板的基板支架。
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公开(公告)号：US11354476B2
公开(公告)日：2022-06-07
申请号：US16682187
申请日：2019-11-13
申请人： Hiroshi Watanabe
发明人： Nobuyuki Sano , Hiroshi Watanabe , Chih-Wei Yao
IPC分类号： G06F17/10 , G06F30/367 , G06F111/08
摘要： There is a significant precaution when performing random dopant fluctuation by using the drift-diffusion model that is the basis of the conventional device simulation. Because the continuation by a long wavelength approximation was done to derive said drift-diffusion model. That is how to recover the location dependence of discrete impurity ions in the long wavelength approximation. For example, in the case that there is an impurity ion near to the interface to an insulating film, the charge density of an impurity ion, which was made continuous in the conventional method, is unable to catch the charge density change due to polarization at the interface. Because this polarization is dependent of the location of a discrete impurity ion near to the interface.
A method for simply implementing the effect of polarization to the device simulation is provided by appending an image charge inside the insulating film to linearize the charge of discrete impurity ion which locates near to the interface to satisfy the consistency to the drift-diffusion model while keeping the location dependency of the discrete ion.-
公开(公告)号：US10785022B2
公开(公告)日：2020-09-22
申请号：US15700280
申请日：2017-09-11
申请人： Hiroshi Watanabe
摘要： A network includes a logical network and a physical network. The logical network includes a plurality of logical nodes. Each logical node is connected to a respective identification core. Each identification core includes at least one semiconductor chip having a physical randomness. Each semiconductor chip generates one of a plurality of pairs of private keys and public keys based on the physical randomness thereof according to an input received by the one of the at least one semiconductor chip under a public key cryptography. One of the public keys is regarded as a logical address of one of the logical nodes, which is connected to one of the identification cores. The physical network includes a plurality of physical nodes. Each identification core is one of components in each physical node. The logical network is uniquely linked to the physical network by the pairs of private keys and public keys.
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公开(公告)号：US10693636B2
公开(公告)日：2020-06-23
申请号：US15871178
申请日：2018-01-15
申请人： Guigen Xia , Hiroshi Watanabe
摘要： An authenticated network having a plurality of nodes is disclosed. Each node includes a transaction unit and an identification core. The identification core includes a key generator. The key generators of the identification cores generate a plurality of unique pairs of secret and public keys. The public key serves as a logical address of the transaction unit. Another authenticated network having a plurality of nodes is also disclosed, in which the identification core further includes a private key. The key generators of the identification cores generate a plurality of public keys from the private keys of the identification cores. Each public key serves as a logical address of the transaction unit of a corresponding node. One of the public keys and one of the private keys form a unique pair. Thus, the transaction unit manages the information communication among the plurality of nodes. The identification core manages an authentication of the nodes.
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公开(公告)号：US10460824B2
公开(公告)日：2019-10-29
申请号：US15416160
申请日：2017-01-26
申请人： Hiroshi Watanabe
IPC分类号： G11C29/34 , G11C29/02 , G11C29/00 , G06F21/57 , G11C29/18 , G06F21/44 , G06F21/73 , G11C7/24 , G09C1/00 , G11C29/12 , G11C29/16 , G11C29/24 , G11C29/26 , G11C29/36 , G11C29/44 , G11C29/56 , H04L9/08 , H04L9/32
摘要： A semiconductor apparatus includes a semiconductor chip, with the semiconductor chip including a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region. The distribution of the retrieved redundant addresses is irreversible, with a random number representing physical properties intrinsic to the semiconductor chip and providing copy protection. When another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction. The test circuit outputs a random number generated from the distribution of the retrieved redundant addresses according to a specification code received from a physical-chip-identification measuring device.
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公开(公告)号：US10177923B2
公开(公告)日：2019-01-08
申请号：US15643617
申请日：2017-07-07
申请人： Hiroshi Watanabe
IPC分类号： H04L9/08 , H04L9/32 , G06F7/58 , G06F21/44 , G06F21/60 , G06F21/70 , G06F21/73 , G06F21/86 , H01L23/535 , H01L27/108 , H04L12/24 , G11C7/24 , G11C13/00 , G11C16/20 , G11C16/22 , G11C11/22 , G11C11/16 , H04L29/06 , G11C29/44
摘要： A network of electronic appliances includes a plurality of network units of electronic appliances. The network units include a first network unit and a plurality of second network units. The first network unit is connected to at least one of the second network units. Each of the network units includes a stem server and a plurality of peripheral devices connected to the stem server. The stem server includes at least one passcode and at least one list of a plurality of registration codes. Each list is associated to a respective passcode. Each registration code of one list associating to one passcode corresponds to a respective peripheral device. Each registration code is generated in response to a respective passcode using physical randomness of a respective peripheral device in correspondence to the passcode. An address of each identification cell is defined by several word lines and bit lines.
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