公开(公告)号：US07910464B2

公开(公告)日：2011-03-22

申请号：US12695759

申请日：2010-01-28

Applicant: Tomohiro Murata ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

Inventor： Tomohiro Murata ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L29/66871 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/8128

Abstract: A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.

Abstract translation: 本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。 深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

公开(公告)号：US07800097B2

公开(公告)日：2010-09-21

申请号：US11299818

申请日：2005-12-13

Applicant: Yutaka Hirose ,  Tsuyoshi Tanaka

Inventor： Yutaka Hirose ,  Tsuyoshi Tanaka

IPC: H01L21/00 ,  H01L29/06 ,  H01L31/072

CPC classification number: H01L27/0605 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.

Abstract translation: 半导体器件包括n型硅的半导体衬底，在其上部包括彼此间隔开并掺杂有p型杂质的第一极性反转区域和第二极性反转区域。 包括第一有源层的第一HFET和包括由III-V族氮化物半导体构成的第二有源层的第二HFET独立地形成在半导体衬底中的相应极性反转区域上，并且HFET彼此电连接 通过互连。

公开(公告)号：US07553747B2

公开(公告)日：2009-06-30

申请号：US11495454

申请日：2006-07-31

Applicant: Yutaka Hirose ,  Tsuyoshi Tanaka

Inventor： Yutaka Hirose ,  Tsuyoshi Tanaka

IPC: H01L29/74

CPC classification number: H01L29/872 ,  H01L29/2003 ,  H01L29/66143

Abstract: A Schottky diode includes a first nitride semiconductor layer formed on a substrate and a second nitride semiconductor layer selectively formed on the first nitride semiconductor layer and having a different conductivity type from that of the first nitride semiconductor layer. A Schottky electrode is selectively formed on the first nitride semiconductor layer to come into contact with the top surface of the second nitride semiconductor layer, and an ohmic electrode is formed thereon so as to be spaced apart from the Schottky electrode.

Abstract translation: 肖特基二极管包括形成在衬底上的第一氮化物半导体层和选择性地形成在第一氮化物半导体层上并且具有与第一氮化物半导体层的导电类型不同的导电类型的第二氮化物半导体层。 肖特基电极选择性地形成在第一氮化物半导体层上以与第二氮化物半导体层的顶表面接触，并且在其上形成欧姆电极以与肖特基电极间隔开。

公开(公告)号：US20090050937A1

公开(公告)日：2009-02-26

申请号：US12257807

申请日：2008-10-24

Applicant: Tomohiro MURATA ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

Inventor： Tomohiro MURATA ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC: H01L29/778

CPC classification number: H01L29/66871 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/8128

Abstract: A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.

Abstract translation: 本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。 深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

公开(公告)号：US07339207B2

公开(公告)日：2008-03-04

申请号：US11455631

申请日：2006-06-20

Applicant: Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

Inventor： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC: H01L31/0328

CPC classification number: H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

Abstract: A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

Abstract translation: 半导体器件具有：形成在导电衬底上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N构成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。

公开(公告)号：US07217960B2

公开(公告)日：2007-05-15

申请号：US11325340

申请日：2006-01-05

Applicant: Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

Inventor： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC: H01L33/00

CPC classification number: H01L29/7786 ,  H01L29/2003

Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

Abstract translation: 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小 可以实现。

公开(公告)号：US07187014B2

公开(公告)日：2007-03-06

申请号：US10862452

申请日：2004-06-08

Applicant: Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

Inventor： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

IPC: H01L29/772

CPC classification number: H01L29/7787 ,  H01L29/2003

Abstract: A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

Abstract translation: 半导体器件具有蓝宝石衬底，设置在蓝宝石衬底上的由GaN制成的半导体层，设置在半导体层上的多层膜和与该多层膜欧姆接触的电极。 已经通过交替地堆叠具有不同量的极化或不同量的自发极化的两种类型的半导体层，并且每个含有n型杂质，以便在两种类型的半导体层之间的界面处诱导电子而形成多层膜。 这允许电极和多层膜之间的接触电阻和电流传输路径中的寄生电阻降低到比常规半导体器件中的值更低的值。

公开(公告)号：US07026261B2

公开(公告)日：2006-04-11

申请号：US10861464

申请日：2004-06-07

Applicant: Yutaka Hirose ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Yutaka Hirose ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L21/26

CPC classification number: H01L21/30612 ,  H01L21/78

Abstract: A semiconductor layer formed on one surface of a substrate is irradiated with light from the other surface of the substrate to thermally decompose part of a region of the semiconductor layer in contact with the substrate, thereby forming a thermally decomposed layer. Thereafter, the thermally decomposed layer is removed with the substrate kept bonded with the semiconductor layer.

Abstract translation: 在基板的一个表面上形成的半导体层被照射来自基板的另一个表面的光，以热分解半导体层与基板接触的区域的一部分，从而形成热分解层。 之后，用与半导体层保持接合的基板去除热分解层。

公开(公告)号：US20070254419A1

公开(公告)日：2007-11-01

申请号：US11819198

申请日：2007-06-26

Applicant: Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

Inventor： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

IPC: H01L21/338

CPC classification number: H01L29/7787 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14656 ,  H01L29/2003 ,  H01L29/66462

Abstract: A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.

公开(公告)号：US07238970B2

公开(公告)日：2007-07-03

申请号：US10971098

申请日：2004-10-25

Applicant: Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

Inventor： Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC: H01L29/732

CPC classification number: H01L21/28575 ,  C30B25/02 ,  C30B29/40 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/802 ,  H01L33/32 ,  H01L33/40

Abstract: A semiconductor device of the present invention comprises a Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity and at least one ohmic electrode formed on the Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity. The ohmic electrode is formed of a conductive material containing a metal boride.

Abstract translation: 本发明的半导体器件包括具有n型导电性的氮化镓等的III-V族氮化物半导体层和形成在氮化镓等的III-V族氮化物半导体层上的至少一个欧姆电极， n型电导率。 欧姆电极由含有金属硼化物的导电材料形成。