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1.发明申请Method for determining low-noise power spectral density for characterizing line edge roughness in semiconductor wafer processing 失效确定用于表征半导体晶片处理中的线边缘粗糙度的低噪声功率谱密度的方法公开(公告)号：US20080194046A1
公开(公告)日：2008-08-14
申请号：US11706118
申请日：2007-02-13
申请人： Yuansheng Ma , Harry J. Levinson , Thomas Wallow
发明人： Yuansheng Ma , Harry J. Levinson , Thomas Wallow
IPC分类号： H01L21/66
CPC分类号： G03F7/70625 , G03F7/705 , G03F7/70616
摘要： According to one exemplary embodiment, a method for determining a power spectral density of an edge of at least one patterned feature situated over a semiconductor wafer includes measuring the edge of the at least one patterned feature at a number of points on the edge. The method further includes determining an autoregressive estimation of the edge of the at least one patterned feature using measured data corresponding to a number of points on the edge. The method further includes determining a power spectral density of the edge using autoregressive coefficients from the autoregressive estimation. The method further includes utilizing the power spectral density to characterize line edge roughness of the at least one patterned feature in a frequency domain.
摘要翻译： 根据一个示例性实施例，用于确定位于半导体晶片之上的至少一个图案化特征的边缘的功率谱密度的方法包括在边缘上的多个点处测量所述至少一个图案化特征的边缘。 该方法还包括使用对应于边缘上的多个点的测量数据来确定至少一个图案化特征的边缘的自回归估计。 该方法还包括使用来自自回归估计的自回归系数确定边缘的功率谱密度。 该方法还包括利用功率谱密度来表征频域中的至少一个图案化特征的线边缘粗糙度。
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2.发明授权Method for determining low-noise power spectral density for characterizing line edge roughness in semiconductor wafer processing 失效确定用于表征半导体晶片处理中的线边缘粗糙度的低噪声功率谱密度的方法公开(公告)号：US08067252B2
公开(公告)日：2011-11-29
申请号：US11706118
申请日：2007-02-13
申请人： Yuansheng Ma , Harry J. Levinson , Thomas Wallow
发明人： Yuansheng Ma , Harry J. Levinson , Thomas Wallow
IPC分类号： H01L21/66
CPC分类号： G03F7/70625 , G03F7/705 , G03F7/70616
摘要： According to one exemplary embodiment, a method for determining a power spectral density of an edge of at least one patterned feature situated over a semiconductor wafer includes measuring the edge of the at least one patterned feature at a number of points on the edge. The method further includes determining an autoregressive estimation of the edge of the at least one patterned feature using measured data corresponding to a number of points on the edge. The method further includes determining a power spectral density of the edge using autoregressive coefficients from the autoregressive estimation. The method further includes utilizing the power spectral density to characterize line edge roughness of the at least one patterned feature in a frequency domain.
摘要翻译： 根据一个示例性实施例，用于确定位于半导体晶片之上的至少一个图案化特征的边缘的功率谱密度的方法包括在边缘上的多个点处测量所述至少一个图案化特征的边缘。 该方法还包括使用与边缘上的多个点对应的测量数据来确定至少一个图案化特征的边缘的自回归估计。 该方法还包括使用来自自回归估计的自回归系数确定边缘的功率谱密度。 该方法还包括利用功率谱密度来表征频域中的至少一个图案化特征的线边缘粗糙度。
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3.发明申请Method for forming a high resolution resist pattern on a semiconductor wafer 有权在半导体晶片上形成高分辨率抗蚀剂图案的方法公开(公告)号：US20080233494A1
公开(公告)日：2008-09-25
申请号：US11726433
申请日：2007-03-22
IPC分类号： G03C11/00
CPC分类号： G03F7/38
摘要： In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.
摘要翻译： 在一个公开的实施例中，在半导体晶片上形成高分辨率抗蚀剂图案的方法包括在半导体晶片上形成的材料层上形成包含例如聚合物基质和催化物质的抗蚀剂层; 将抗蚀剂层暴露于图案化辐射; 以及在后曝光烘烤处理期间向半导体晶片施加磁场。 在一个实施例中，图案化的辐射由极紫外（EUV）光源提供。 在其它实施例中，图案化辐射源可以是例如电子束或离子束。 在一个实施方案中，聚合物基质是有机聚合物基质，例如苯乙烯，丙烯酸酯或甲基丙烯酸酯。 在一个实施方案中，催化物质可以是例如酸，碱或氧化剂。
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4.发明授权Shape characterization with elliptic fourier descriptor for contact or any closed structures on the chip 有权形状表征与椭圆形的描述符接触或芯片上的任何封闭结构公开(公告)号：US08367430B2
公开(公告)日：2013-02-05
申请号：US12575068
申请日：2009-10-07
申请人： Yuansheng Ma , Harry J. Levinson , Jongwook Kye
发明人： Yuansheng Ma , Harry J. Levinson , Jongwook Kye
IPC分类号： H01L21/66
CPC分类号： G06F17/5081 , G06F2217/10
摘要： Shapes and orientations of contacts or other closed contours on an integrated circuit are characterized by calculating Elliptic Fourier descriptors. The descriptors are then used for generating design rules for the integrated circuit and for assessing process capability for the manufacturing of the integrated circuit. Monte Carlo simulation can be performed in conjunction with the elliptic Fourier descriptors.
摘要翻译： 集成电路上触点或其他封闭轮廓的形状和方向的特征在于计算椭圆傅立叶描述符。 然后将描述符用于生成集成电路的设计规则并用于评估集成电路制造的处理能力。 可以与椭圆傅立叶描述符一起执行蒙特卡罗模拟。
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5.发明授权Method for forming a high resolution resist pattern on a semiconductor wafer 有权在半导体晶片上形成高分辨率抗蚀剂图案的方法公开(公告)号：US08586269B2
公开(公告)日：2013-11-19
申请号：US11726433
申请日：2007-03-22
IPC分类号： G11B11/105
CPC分类号： G03F7/38
摘要： In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.
摘要翻译： 在一个公开的实施例中，在半导体晶片上形成高分辨率抗蚀剂图案的方法包括在半导体晶片上形成的材料层上形成包含例如聚合物基质和催化物质的抗蚀剂层; 将抗蚀剂层暴露于图案化辐射; 以及在后曝光烘烤处理期间向半导体晶片施加磁场。 在一个实施例中，图案化的辐射由极紫外（EUV）光源提供。 在其它实施例中，图案化辐射源可以是例如电子束或离子束。 在一个实施方案中，聚合物基质是有机聚合物基质，例如苯乙烯，丙烯酸酯或甲基丙烯酸酯。 在一个实施方案中，催化物质可以是例如酸，碱或氧化剂。
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6.发明授权Methods of forming contacts for semiconductor devices using a local interconnect processing scheme 有权使用局部互连处理方案形成用于半导体器件的触点的方法公开(公告)号：US08809184B2
公开(公告)日：2014-08-19
申请号：US13465633
申请日：2012-05-07
申请人： Lei Yuan , Jin Cho , Jongwook Kye , Harry J. Levinson
发明人： Lei Yuan , Jin Cho , Jongwook Kye , Harry J. Levinson
IPC分类号： H01L21/762 , H01L21/768 , H01L21/8238 , H01L21/441 , H01L23/535
CPC分类号： H01L21/823475 , H01L21/76895 , H01L23/485 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.
摘要翻译： 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。
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7.发明授权公开(公告)号：US08338061B2
公开(公告)日：2012-12-25
申请号：US13158234
申请日：2011-06-10
IPC分类号： G03F1/00
摘要： Fluorine-passivated reticles for use in lithography and methods for fabricating and using such reticles are provided. According to one embodiment, a method for performing photolithography comprises placing a fluorine-passivated reticle between an illumination source and a target semiconductor wafer and causing electromagnetic radiation to pass from the illumination source through the fluorine-passivated reticle to the target semiconductor wafer. In another embodiment, a fluorine-passivated reticle comprises a substrate and a patterned fluorine-passivated absorber material layer overlying the substrate. According to another embodiment, a method for fabricating a reticle for use in photolithography comprises providing a substrate and forming a fluorine-passivated absorber material layer overlying the substrate.
摘要翻译： 提供用于光刻的氟钝化的掩模版以及制造和使用这种掩模版的方法。 根据一个实施例，一种用于执行光刻的方法包括在照明源和目标半导体晶片之间放置氟钝化的掩模版，并使电磁辐射从照明源通过氟钝化掩模版到达目标半导体晶片。 在另一个实施例中，氟钝化的掩模版包括衬底和覆盖衬底的图案化的氟钝化吸收材料层。 根据另一实施例，一种用于光刻中使用的掩模版的制造方法包括提供基板并形成覆盖在基板上的氟钝化的吸收材料层。
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公开(公告)号：US20080198453A1
公开(公告)日：2008-08-21
申请号：US11709718
申请日：2007-02-21
IPC分类号： G02B5/30
CPC分类号： G02B5/3058 , G02B5/3075 , G02F1/0136 , G03F7/70566
摘要： According to one exemplary embodiment, an optical polarizer positioned before a light source for use in semiconductor wafer lithography includes an array of aligned nanotubes. The array of aligned nanotubes cause light emitted from the light source and incident on the array of aligned nanotubes to be converted into polarized light for use in the semiconductor wafer lithography. The amount of polarization can be controlled by a voltage source coupled to the array of aligned nanotubes. Chromogenic material of a light filtering layer can vary the wavelength of the polarized light transmitted through the array of aligned nanotubes.
摘要翻译： 根据一个示例性实施例，定位在用于半导体晶片光刻的光源之前的光学偏振器包括排列的纳米管阵列。 排列的纳米管的阵列引起从光源发射并入射到排列的纳米管阵列上的光，以转换为偏光，用于半导体晶片光刻。 极化量可以通过耦合到排列的纳米管阵列的电压源来控制。 光过滤层的显色材料可以改变通过排列的纳米管阵列传输的偏振光的波长。
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9.发明授权Method and apparatus for monitoring and controlling imaging in immersion lithography systems 有权浸没光刻系统中成像监测和控制的方法和装置公开(公告)号：US07006209B2
公开(公告)日：2006-02-28
申请号：US10628021
申请日：2003-07-25
申请人： Harry J. Levinson
发明人： Harry J. Levinson
IPC分类号： G01N21/41
CPC分类号： G03F7/70341
摘要： A method of monitoring an immersion lithography system in which a wafer can be immersed in a liquid immersion medium. The method detects an index of refraction of the immersion medium in a volume of the immersion medium through which an exposure pattern is configured to traverse and determines if the index of refraction is acceptable for exposing the wafer with the exposure pattern. Also disclosed is a monitoring and control system for an immersion lithography system.
摘要翻译： 一种监测浸没式光刻系统的方法，其中晶片可浸入浸液介质中。 该方法检测浸没介质的体积中的曝光折射率，曝光图案通过该浸渍介质体积穿过，并确定折射率是否可接受，以便用曝光图案曝光晶片。 还公开了一种用于浸没式光刻系统的监视和控制系统。
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公开(公告)号：US06593037B1
公开(公告)日：2003-07-15
申请号：US09847803
申请日：2001-05-02
IPC分类号： G03F900
摘要： A reflective mask or reticle configured to reduce reflections from an absorptive layer during lithography at a wavelength shorter than in a deep ultraviolet (DUV) range is disclosed herein. The reflective mask or reticle is configured to generate additional reflections which have a desirable phase difference with respect to the reflections from the absorptive layer. The additional reflections reduce or eliminate the reflections from the absorptive layer by destructive interference.
摘要翻译： 本文公开了一种反射掩模或掩模版，其被配置为在光刻期间以比在深紫外（DUV）范围内的波长短的波长来减少来自吸收层的反射。 反射掩模或掩模版被配置为产生相对于来自吸收层的反射具有期望的相位差的附加反射。 附加的反射通过相消干涉减少或消除了吸收层的反射。
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