公开(公告)号：US20130170303A1

公开(公告)日：2013-07-04

申请号：US13610810

申请日：2012-09-11

Applicant: Young-Soo AHN ,  Jong-Moo Choi ,  Yoo-Hyun Noh

Inventor： Young-Soo AHN ,  Jong-Moo Choi ,  Yoo-Hyun Noh

IPC: H01L29/78 ,  G11C16/04

CPC classification number: H01L29/792 ,  H01L27/11578 ,  H01L29/66833

Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.

Abstract translation: 非易失性存储器件包括形成在衬底上并包括交替层叠有多个沟道层的多个层间电介质层的多个沟道结构; 第一和第二垂直栅极，沿着与沟道结构交叉的一个方向交替地布置在沟道结构之间，并且与介于其间的存储层相邻; 以及设置在所述通道结构之上或之下的一对第一和第二字线，并且沿着所述一个方向延伸以与所述第一和第二垂直门重叠。 第一字线与第一垂直门连接，第二字线与第二垂直门连接。

公开(公告)号：US08687425B2

公开(公告)日：2014-04-01

申请号：US13610810

申请日：2012-09-11

Applicant: Young-Soo Ahn ,  Jong-Moo Choi ,  Yoo-Hyun Noh

Inventor： Young-Soo Ahn ,  Jong-Moo Choi ,  Yoo-Hyun Noh

IPC: G11C11/34 ,  G11C16/04 ,  G11C5/02 ,  G11C5/06

CPC classification number: H01L29/792 ,  H01L27/11578 ,  H01L29/66833

Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.

Abstract translation: 非易失性存储器件包括形成在衬底上并包括交替层叠有多个沟道层的多个层间电介质层的多个沟道结构; 第一和第二垂直栅极，沿着与沟道结构交叉的一个方向交替地布置在沟道结构之间，并且与介于其间的存储层相邻; 以及设置在所述通道结构之上或之下的一对第一和第二字线，并且沿着所述一个方向延伸以与所述第一和第二垂直门重叠。 第一字线与第一垂直门连接，第二字线与第二垂直门连接。

公开(公告)号：US08797797B2

公开(公告)日：2014-08-05

申请号：US13606818

申请日：2012-09-07

Applicant: Yoo-Hyun Noh

Inventor： Yoo-Hyun Noh

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11524 ,  H01L29/66825

Abstract: A non-volatile memory device includes a first string and a second string that each include a first drain selection transistor, a second drain selection transistor, a plurality of memory cells, and a source selection transistor that are coupled in series in that order, respectively, a first bit line coupled with a node between the first and second drain selection transistors of the first string, and a second bit line coupled with an end node of the second string on the side of the first drain selection transistor of the second string, wherein gates of the first drain selection transistors of the first and second strings are coupled with each other, and gates of the second drain selection transistors of the first and second strings are coupled with each other.

Abstract translation: 非易失性存储器件包括第一串和第二串，每个第一串和第二串分别包括以该顺序串联耦合的第一漏极选择晶体管，第二漏极选择晶体管，多个存储器单元和源极选择晶体管 与第一串的第一和第二漏极选择晶体管之间的节点耦合的第一位线以及与第二串的第一漏极选择晶体管侧的第二串的端部节点耦合的第二位线， 其中所述第一和第二串的所述第一漏极选择晶体管的栅极彼此耦合，并且所述第一和第二串联的第二漏极选择晶体管的栅极彼此耦合。