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    Memory device having a duty ratio corrector
    1.
    发明授权
    Memory device having a duty ratio corrector 有权
    具有占空比校正器的存储器件

    公开(公告)号：US07190203B2

    公开(公告)日：2007-03-13

    申请号：US11336058

    申请日：2006-01-20

    申请人： Young Bae Choi ,  Kwang Jin Na

    发明人： Young Bae Choi ,  Kwang Jin Na

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K5/151

    摘要： A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

    摘要翻译： 一种具有占空比校正器的存储器件，该占空比校正器可以通过施加用于关闭用于产生用于校正初始阶段的占空比的辅助电压的开关器件的输入信号来阻断输出端子与接地端子之间的电流路径来降低功耗，以及哪个 可以通过将辅助电压从预定电压而不是0V改变到目标电压来提高操作速度。

    Circuit for Generating Data Strobe Signal in DDR Memory Device and Method Therefor
    2.
    发明申请
    Circuit for Generating Data Strobe Signal in DDR Memory Device and Method Therefor 有权
    用于在DDR存储器件中产生数据选通信号的电路及其方法

    公开(公告)号：US20100172196A1

    公开(公告)日：2010-07-08

    申请号：US12727185

    申请日：2010-03-18

    申请人： Kwang Jin Na ,  Young Bae Choi

    发明人： Kwang Jin Na ,  Young Bae Choi

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

    摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

    摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

    Memory device having a duty ratio corrector
    3.
    发明授权
    Memory device having a duty ratio corrector 有权

    公开(公告)号：US07312647B2

    公开(公告)日：2007-12-25

    申请号：US11623927

    申请日：2007-01-17

    申请人： Young Bae Choi ,  Kwang Jin Na

    发明人： Young Bae Choi ,  Kwang Jin Na

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K5/151

    摘要： A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

    Circuit for generating data strobe signal in DDR memory device and method therefor
    4.
    发明授权
    Circuit for generating data strobe signal in DDR memory device and method therefor 有权
    用于在DDR存储器件中产生数据选通信号的电路及其方法

    公开(公告)号：US07983101B2

    公开(公告)日：2011-07-19

    申请号：US12727185

    申请日：2010-03-18

    申请人： Kwang Jin Na ,  Young Bae Choi

    发明人： Kwang Jin Na ,  Young Bae Choi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

    摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

    摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

    Circuit for generating data strobe in DDR memory device, and method therefor
    5.
    发明授权
    Circuit for generating data strobe in DDR memory device, and method therefor 有权
    用于在DDR存储器件中产生数据选通的电路及其方法

    公开(公告)号：US07710799B2

    公开(公告)日：2010-05-04

    申请号：US11611922

    申请日：2006-12-18

    申请人： Kwang Jin Na ,  Young Bae Choi

    发明人： Kwang Jin Na ,  Young Bae Choi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

    摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

    摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下根据CAS等待时间使用内部时钟信号，并且通过使用脉冲来产生数据选通信号，并且通过利用内部时钟信号精确地控制操作定时，可以提高电路操作的可靠性。

    Circuit for generating data strobe signal in DDR memory device, and method therefor
    6.
    发明授权
    Circuit for generating data strobe signal in DDR memory device, and method therefor 有权
    用于在DDR存储器件中产生数据选通信号的电路及其方法

    公开(公告)号：US07173866B2

    公开(公告)日：2007-02-06

    申请号：US10879878

    申请日：2004-06-29

    申请人： Kwang Jin Na ,  Young Bae Choi

    发明人： Kwang Jin Na ,  Young Bae Choi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

    摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

    摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

    Duty ratio corrector, and memory device having the same
    7.
    发明授权
    Duty ratio corrector, and memory device having the same 有权
    占空比校正器和具有该占空比校正器的存储器件

    公开(公告)号：US07023254B2

    公开(公告)日：2006-04-04

    申请号：US10878769

    申请日：2004-06-28

    申请人： Young Bae Choi ,  Kwang Jin Na

    发明人： Young Bae Choi ,  Kwang Jin Na

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  H03K5/151

    摘要： The present invention discloses a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to an target voltage, and a memory device having the same.

    摘要翻译： 本发明公开了一种占空比校正器，其通过施加用于关闭用于产生用于校正初始阶段的占空比的辅助电压的开关器件的输入信号来阻断输出端子与接地端子之间的电流路径来降低功耗，以及哪个 可以通过将辅助电压从预定电压（而不是0V）改变到目标电压来提高操作速度，以及具有其的存储器件。

    Delay locked loop (DLL) circuit for generating clock signal for memory device
    8.
    发明授权
    Delay locked loop (DLL) circuit for generating clock signal for memory device 失效
    延迟锁定环路（DLL）电路，用于产生存储器件的时钟信号

    公开(公告)号：US07605624B2

    公开(公告)日：2009-10-20

    申请号：US11824840

    申请日：2007-06-29

    申请人： Kwang Jin Na

    发明人： Kwang Jin Na

    IPC分类号： H03L7/06

    CPC分类号： H03L7/07 ,  H03L7/0812

    摘要： A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock signals by a predetermined period of time in response to a first control signal, and generate a plurality of first internal clock signals and a second delay locked loop (DLL) configured to receive the first internal clock signals, delay the first internal clock signals by a predetermined period of time in response to a second control signal, and generate a plurality of second internal clock signals.

    摘要翻译： 公开了一种延迟锁定环（DLL）电路。 DLL电路包括被配置为接收多个第一时钟信号的第一延迟锁定环（DLL），响应于第一控制信号将每个第一时钟信号延迟预定的时间段，并且产生多个第一内部 时钟信号和第二延迟锁定环（DLL），被配置为接收第一内部时钟信号，响应于第二控制信号将第一内部时钟信号延迟预定时间段，并产生多个第二内部时钟信号。

    DATA OUTPUT CIRCUIT IN SEMICONDUCTOR MEMORY APPARATUS
    9.
    发明申请
    DATA OUTPUT CIRCUIT IN SEMICONDUCTOR MEMORY APPARATUS 有权
    半导体存储器中的数据输出电路

    公开(公告)号：US20090168548A1

    公开(公告)日：2009-07-02

    申请号：US12173724

    申请日：2008-07-15

    申请人： Kwang Jin Na

    发明人： Kwang Jin Na

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1066

    摘要： A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data.

    摘要翻译： 半导体存储装置中的数据输出电路包括：第一数据驱动单元，被配置为在第一定时产生第一驱动数据;第一缓冲单元，被配置为通过缓冲第一驱动数据产生第一输出数据;第二数据驱动单元 被配置为在与第一定时不同的第二定时产生第二驱动数据，以及第二缓冲单元，被配置为通过缓冲第二驱动数据来生成第二输出数据。

    Duty cycle correction circuit
    10.
    发明授权
    Duty cycle correction circuit 有权
    占空比校正电路

    公开(公告)号：US08390353B2

    公开(公告)日：2013-03-05

    申请号：US13332964

    申请日：2011-12-21

    申请人： Dong Suk Shin ,  Kwang Jin Na

    发明人： Dong Suk Shin ,  Kwang Jin Na

    IPC分类号： H03K3/017

    CPC分类号： H03K5/04

    摘要： A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

    摘要翻译： 占空比校正电路包括占空比校正块，其被配置为响应于占空比代码和输入信号产生第一预校正信号和第二预校正信号; 配置为响应于第一选择信号，第二选择信号，第一预校正信号和第二预校正信号产生占空比校正信号的占空比校正信号产生块; 以及控制块，被配置为响应于占空比校正信号和输入信号而产生占空比代码，第一选择信号和第二选择信号。