公开(公告)号：US08390350B2

公开(公告)日：2013-03-05

申请号：US12845416

申请日：2010-07-28

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/0816

摘要： A clock signal delay circuit includes a variable delay unit, a delay unit, a phase detection block, a control clock output block, and a delay control unit. The variable delay unit controls a delay amount of a reference clock signal based on a delay control signal and provides a delayed clock signal based thereon. The delay unit delays the delayed clock signal and provides a feedback clock signal based thereon. The phase detection block detects a phase difference between the feedback clock signal and the reference clock signal and provides a detected phase difference based thereon. The control clock output block provides a control clock signal based on the detected phase difference. The delay control unit generates the delay control signal based on the detected phase difference and in response to the control clock signal.

摘要翻译： 时钟信号延迟电路包括可变延迟单元，延迟单元，相位检测块，控制时钟输出块和延迟控制单元。 可变延迟单元基于延迟控制信号控制参考时钟信号的延迟量，并且基于延迟控制信号提供延迟的时钟信号。 延迟单元延迟延迟的时钟信号并且基于此提供反馈时钟信号。 相位检测块检测反馈时钟信号和参考时钟信号之间的相位差，并基于此检测相位差。 控制时钟输出块基于检测到的相位差提供控制时钟信号。 延迟控制单元根据所检测的相位差和响应于控制时钟信号产生延迟控制信号。

公开(公告)号：US20130002323A1

公开(公告)日：2013-01-03

申请号：US13332964

申请日：2011-12-21

申请人： Dong Suk SHIN ,  Kwang Jin NA

发明人： Dong Suk SHIN ,  Kwang Jin NA

IPC分类号： H03K5/04

CPC分类号： H03K5/04

摘要： A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

摘要翻译： 占空比校正电路包括占空比校正块，其被配置为响应于占空比代码和输入信号产生第一预校正信号和第二预校正信号; 配置为响应于第一选择信号，第二选择信号，第一预校正信号和第二预校正信号产生占空比校正信号的占空比校正信号产生块; 以及控制块，被配置为响应于占空比校正信号和输入信号而产生占空比代码，第一选择信号和第二选择信号。

公开(公告)号：US08344775B2

公开(公告)日：2013-01-01

申请号：US12774602

申请日：2010-05-05

申请人： Kwang-Jin Na

发明人： Kwang-Jin Na

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  H03K2005/00052

摘要： A semiconductor device includes an on-die termination circuit, a clock input unit, a clock phase mixing unit, and a data input/output unit. The on-die termination circuit is configured to calibrate a resistance of a termination pad and output an impedance matching code. The clock input unit is configured to receive a data clock. The clock phase mixing unit is configured to receive the data clock through the clock input unit and a delayed data clock, which is generated by delaying the data clock by a predetermined time, mix a phase of the data clock and a phase of the delayed data clock at a ratio corresponding to the impedance matching code, and output a phase-mixed data clock. The data input/output unit is configured to input/output a data signal in response to the phase-mixed data clock.

摘要翻译： 半导体器件包括片上终端电路，时钟输入单元，时钟相位混合单元和数据输入/输出单元。 片上终端电路被配置为校准终端焊盘的电阻并输出阻抗匹配代码。 时钟输入单元被配置为接收数据时钟。 时钟相位混合单元被配置为通过时钟输入单元接收数据时钟，并且通过将数据时钟延迟预定时间而产生的延迟数据时钟，将数据时钟的相位和延迟数据的相位混合 时钟以与阻抗匹配码相对应的比率输出，并输出相位混合数据时钟。 数据输入/输出单元被配置为响应于相位混合数据时钟输入/输出数据信号。

公开(公告)号：US08222934B2

公开(公告)日：2012-07-17

申请号：US13038604

申请日：2011-03-02

申请人： Kwang-Jin Na

发明人： Kwang-Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/087

摘要： A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.

摘要翻译： DLL电路包括：时钟选择控制单元，被配置为基于参考时钟和反馈时钟之间的相位差产生时钟选择信号，并且在产生时钟选择信号之后生成初始化信号。 延迟控制单元，当初始化信号被使能时，通过将外部电源电压分配为延迟单元作为控制电压来传送要产生的初始电压，并且控制在所选择的延迟基准时钟的延迟操作 时钟选择信号的基础。

公开(公告)号：US07983101B2

公开(公告)日：2011-07-19

申请号：US12727185

申请日：2010-03-18

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US07800957B2

公开(公告)日：2010-09-21

申请号：US12173724

申请日：2008-07-15

申请人： Kwang-Jin Na

发明人： Kwang-Jin Na

IPC分类号： G11C16/04

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1066

摘要： A data output circuit in a semiconductor memory apparatus includes a first data driving unit configured to generate a first driving data at a first timing, a first buffering unit configured to generate a first output data by buffering the first driving data, a second data driving unit configured to generate a second driving data at a second timing that is different from the first timing, and a second buffering unit configured to generate a second output data by buffering the second driving data.

摘要翻译： 半导体存储装置中的数据输出电路包括：第一数据驱动单元，被配置为在第一定时产生第一驱动数据;第一缓冲单元，被配置为通过缓冲第一驱动数据产生第一输出数据;第二数据驱动单元 被配置为在与第一定时不同的第二定时产生第二驱动数据，以及第二缓冲单元，被配置为通过缓冲第二驱动数据来生成第二输出数据。

公开(公告)号：US07710799B2

公开(公告)日：2010-05-04

申请号：US11611922

申请日：2006-12-18

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下根据CAS等待时间使用内部时钟信号，并且通过使用脉冲来产生数据选通信号，并且通过利用内部时钟信号精确地控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US07492200B2

公开(公告)日：2009-02-17

申请号：US11647904

申请日：2006-12-28

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/093 ,  H03L7/0814 ,  H03L7/089

摘要： A delayed locked loop (DLL) circuit is provided which reliably provides an initial delay period of a delay line.

摘要翻译： 提供延迟锁定环（DLL）电路，其可靠地提供延迟线的初始延迟周期。

公开(公告)号：US20080157837A1

公开(公告)日：2008-07-03

申请号：US11824840

申请日：2007-06-29

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06 ,  H03L7/087

CPC分类号： H03L7/07 ,  H03L7/0812

摘要： A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock signals by a predetermined period of time in response to a first control signal, and generate a plurality of first internal clock signals and a second delay locked loop (DLL) configured to receive the first internal clock signals, delay the first internal clock signals by a predetermined period of time in response to a second control signal, and generate a plurality of second internal clock signals.

摘要翻译： 公开了一种延迟锁定环（DLL）电路。 DLL电路包括被配置为接收多个第一时钟信号的第一延迟锁定环（DLL），响应于第一控制信号将每个第一时钟信号延迟预定的时间段，并且产生多个第一内部 时钟信号和第二延迟锁定环（DLL），被配置为接收第一内部时钟信号，响应于第二控制信号将第一内部时钟信号延迟预定时间段，并产生多个第二内部时钟信号。

公开(公告)号：US20080111595A1

公开(公告)日：2008-05-15

申请号：US11819631

申请日：2007-06-28

申请人： Kwang Jin Na

发明人： Kwang Jin Na

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/087

摘要： A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal.

摘要翻译： DLL电路包括：时钟选择控制单元，被配置为基于参考时钟和反馈时钟之间的相位差产生时钟选择信号，并且在产生时钟选择信号之后生成初始化信号。 延迟控制单元，当初始化信号被使能时，通过将外部电源电压分配为延迟单元作为控制电压来传送要产生的初始电压，并且控制在所选择的延迟基准时钟的延迟操作 时钟选择信号的基础。