公开(公告)号：US07312647B2

公开(公告)日：2007-12-25

申请号：US11623927

申请日：2007-01-17

申请人： Young Bae Choi ,  Kwang Jin Na

发明人： Young Bae Choi ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151

摘要： A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

公开(公告)号：US07190203B2

公开(公告)日：2007-03-13

申请号：US11336058

申请日：2006-01-20

申请人： Young Bae Choi ,  Kwang Jin Na

发明人： Young Bae Choi ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151

摘要： A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

摘要翻译： 一种具有占空比校正器的存储器件，该占空比校正器可以通过施加用于关闭用于产生用于校正初始阶段的占空比的辅助电压的开关器件的输入信号来阻断输出端子与接地端子之间的电流路径来降低功耗，以及哪个 可以通过将辅助电压从预定电压而不是0V改变到目标电压来提高操作速度。

公开(公告)号：US20100172196A1

公开(公告)日：2010-07-08

申请号：US12727185

申请日：2010-03-18

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US07983101B2

公开(公告)日：2011-07-19

申请号：US12727185

申请日：2010-03-18

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US07710799B2

公开(公告)日：2010-05-04

申请号：US11611922

申请日：2006-12-18

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下根据CAS等待时间使用内部时钟信号，并且通过使用脉冲来产生数据选通信号，并且通过利用内部时钟信号精确地控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US07173866B2

公开(公告)日：2007-02-06

申请号：US10879878

申请日：2004-06-29

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US07023254B2

公开(公告)日：2006-04-04

申请号：US10878769

申请日：2004-06-28

申请人： Young Bae Choi ,  Kwang Jin Na

发明人： Young Bae Choi ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151

摘要： The present invention discloses a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to an target voltage, and a memory device having the same.

摘要翻译： 本发明公开了一种占空比校正器，其通过施加用于关闭用于产生用于校正初始阶段的占空比的辅助电压的开关器件的输入信号来阻断输出端子与接地端子之间的电流路径来降低功耗，以及哪个 可以通过将辅助电压从预定电压（而不是0V）改变到目标电压来提高操作速度，以及具有其的存储器件。

公开(公告)号：US06525581B1

公开(公告)日：2003-02-25

申请号：US10033989

申请日：2001-12-28

申请人： Young Bae Choi

发明人： Young Bae Choi

IPC分类号： H03K3017

CPC分类号： H03K5/1565

摘要： The present invention discloses a duty correction circuit for and method of enabling a clock signal and a clock bar signal phase transited from the clock signal by a phase difference of 180° to obtain a duty of 50%. The duty correction circuit includes: a duty check block for determining the duty of a clock signal, and generating a control signal indicating a determination result; and a duty correction block for receiving the clock signal or a clock bar signal, having a phase difference of 180° from the clock signal, correcting the duty of one of the clock signal or the clock bar signal according to the control signal from the duty check block, and outputting the duty-corrected signal. The method includes several steps, which reflect the procedure for correction of the duty.

摘要翻译： 本发明公开了一种用于使时钟信号和时钟信号相位从时钟信号转换180°的相位差的占空比校正电路，以获得占空比为50％。 占空比校正电路包括：用于确定时钟信号的占空比的工作检查块，以及产生指示确定结果的控制信号; 以及用于接收与时钟信号相差180°的时钟信号或时钟条信号的占空比校正块，根据来自占空比的控制信号来校正时钟信号或时钟条信号之一的占空比 检查块，并输出占空比校正信号。 该方法包括几个步骤，反映了更正职责的程序。

公开(公告)号：US07064989B2

公开(公告)日：2006-06-20

申请号：US10879386

申请日：2004-06-29

申请人： Gwang Jin Na ,  Young Bae Choi

发明人： Gwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00

CPC分类号： H04L25/0278

摘要： Provided is directed to an on-die termination control circuit and a method for generating an on-die termination control signal, and the circuit and the method are capable of performing an optimized termination operation during data input and output, by generating a control signal during read and write operations and then controlling the termination circuit to differentiate an impedance of the termination circuit.

摘要翻译： 提供了一种片上终端控制电路和一种用于产生片上终止控制信号的方法，并且电路和方法能够在数据输入和输出期间通过在数字输入和输出期间产生控制信号来执行优化的终止操作 读写操作，然后控制终端电路来区分终端电路的阻抗。

公开(公告)号：US5930298A

公开(公告)日：1999-07-27

申请号：US887169

申请日：1997-07-01

申请人： Young Bae Choi

发明人： Young Bae Choi

IPC分类号： G06F11/10 ,  H03M7/00 ,  H03M13/23 ,  H03M13/41 ,  H04L5/12

CPC分类号： H03M13/6362 ,  H03M13/3961 ,  H03M13/4169

摘要： A Viterbi decoder for decoding depunctured code comprises a branch metric calculation unit; an add/ comparison/ selection unit; a path metric network; a survivor memory unit; a decoding depth control unit; and a decoded symbol selection unit. The decoding depth control unit outputs a decoding depth control signal by determining a decoding depth having the least bit error rate according to code rates of punctured codes. The decoding depth having the least bit error rate is set to a maximum value of integer times or integer+1 times of each code rate's numerators of the punctured codes within a range of a predetermined decoding depth. Accordingly, the Viterbi decoder recovers the original information without the need to expand the conventional survivor memory required for a trace back process in the system using the puncturing technique.

摘要翻译： 用于对经解码的代码进行解码的维特比解码器包括分支度量计算单元; 添加/比较/选择单元; 路径度量网络; 幸存者记忆单位; 解码深度控制单元; 和解码符号选择单元。 解码深度控制单元通过根据穿孔码的码率确定具有最小误码率的解码深度来输出解码深度控制信号。 具有最小误码率的解码深度被设置为在预定解码深度的范围内的每个码率的穿孔码的分子的整数倍或整数+ 1倍的最大值。 因此，维特比解码器恢复原始信息，而不需要扩展使用穿孔技术的系统中的追溯处理所需的常规幸存者存储器。