知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.012 seconds)

    Memory self-refresh re-entry state
    1.
    发明授权
    Memory self-refresh re-entry state 有权

    公开(公告)号：US11914905B1

    公开(公告)日：2024-02-27

    申请号：US17377016

    申请日：2021-07-15

    Applicant: XILINX, INC.

    Inventor： Martin Newman

    IPC: G06F3/06 ,  G06F13/16

    CPC classification number: G06F3/0673 ,  G06F13/1668

    Abstract: Examples describe memory refresh operations for memory subsystems. One example is a method for a memory controller, the method including entering a first state upon exiting self-refresh state, wherein the first state comprises activating a first timer. The method includes entering a second state from the first state upon detecting an end of an active period and detecting that the first timer has not expired. The method includes entering a third state from the second state upon detecting expiration of the second state, wherein the third state comprises re-entering the self-refresh state.

    High bandwidth memory (HBM) bandwidth aggregation switch
    4.
    发明授权
    High bandwidth memory (HBM) bandwidth aggregation switch 有权

    公开(公告)号：US10916516B2

    公开(公告)日：2021-02-09

    申请号：US15616004

    申请日：2017-06-07

    Applicant: Xilinx, Inc.

    Inventor： Martin Newman ,  Sagheer Ahmad

    IPC: H01L23/00 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/16 ,  G06F13/20 ,  H04L12/933 ,  G11C5/06 ,  G11C8/18 ,  G06F13/42 ,  G06F13/40 ,  H01L23/538

    Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to a qualified stacked silicon interconnect (SSI) technology programmable integrated circuit (IC) region by providing an interface (e.g., an HBM buffer region implemented with a hierarchical switch network) between the added feature device and the programmable IC region. One example apparatus generally includes a programmable IC region and an interface region configured to couple the programmable IC region to at least one fixed feature die via a first plurality of ports associated with the at least one fixed feature die and a second plurality of ports associated with the programmable IC region. The interface region is configured as a switch network between the first plurality of ports and the second plurality of ports, and the switch network includes a plurality of full crossbar switch networks.

    Memory controller with reduced latency transaction scheduling
    5.
    发明授权
    Memory controller with reduced latency transaction scheduling 有权

    公开(公告)号：US12045502B1

    公开(公告)日：2024-07-23

    申请号：US17356248

    申请日：2021-06-23

    Applicant: XILINX, INC.

    Inventor： Ygal Arbel ,  Jonathan Jasper ,  Martin Newman

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673

    Abstract: A memory controller includes transaction queue circuitry, a first skip event, a second skip event, a third skip event, and scheduler circuitry. The transaction queue circuitry is configured to store a first transaction, a second transaction, and a third transaction. The first transaction received is by the transaction queue circuitry before the second transaction and the third transaction. The second transaction is received by the transaction queue circuitry before the third transaction. The first skip event counter is associated with the first transaction. The second skip event counter is associated with the second transaction. The third skip event counter is associated with the third transaction. The scheduler circuitry is configured to select the third transaction before selecting the first transaction, increase a value of the first skip event counter based on selecting the third transaction before the first transaction, and communicate the third transaction to a memory device.

Patent Agency Ranking