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    Method and apparatus for direct memory access transfers
    1.
    发明授权
    Method and apparatus for direct memory access transfers 有权

    公开(公告)号：US10853308B1

    公开(公告)日：2020-12-01

    申请号：US16195218

    申请日：2018-11-19

    Applicant: Xilinx, Inc.

    Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Jayaram Pvss ,  Michael Zapke ,  Manjunath Chepuri

    IPC: G06F15/167 ,  G06F15/173 ,  G06F13/28

    Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

    Systems and methods for discovery and configuration of a network device
    4.
    发明授权
    Systems and methods for discovery and configuration of a network device 有权

    公开(公告)号：US11388060B1

    公开(公告)日：2022-07-12

    申请号：US16697144

    申请日：2019-11-26

    Applicant: Xilinx, Inc.

    Inventor： Ramesh R. Subramanian ,  Jayaram Pvss ,  Syed S. Khader

    IPC: G06F15/16 ,  H04L41/12 ,  H04L41/0213 ,  G06F13/28 ,  H04L41/0803 ,  H04L69/324

    Abstract: An integrated circuit (IC) device includes a network device including a first network port, a second network port, and an internal endpoint port. The IC device further includes a first processing unit including an internal end station. The first processing unit is configured to communicate with the network device using the internal endpoint port. The IC device further includes a second processing unit including a bridge management layer. The second processing unit is configured to communicate with the network device using the internal endpoint port. In various embodiments, the first processing unit and the second processing unit are configured to communicate with each other using a first internal channel.

    Scalable tweak engines and prefetched tweak values for encyrption engines
    5.
    发明授权
    Scalable tweak engines and prefetched tweak values for encyrption engines 有权

    公开(公告)号：US12231532B1

    公开(公告)日：2025-02-18

    申请号：US16831356

    申请日：2020-03-26

    Applicant: XILINX, INC.

    Inventor： Devanjan Maiti ,  Robert Bellarmin Susai ,  Jayaram Pvss

    IPC: H04L9/06 ,  G06F9/30 ,  G06F13/28 ,  H04L9/08

    Abstract: Examples herein describe a scalable tweak engine and prefetching tweak values. Regarding the scalable tweak engine, it can be designed to accommodate different bus widths of data. The scalable tweak engine described herein includes multiple tweak calculators that can be daisy chained together to output multiple tweak values every clock cycle. These tweak values can be sent to multiple encryption cores so that multiple data blocks can be encrypted in parallel. Regarding prefetching tweak values, previous encryption engines incur a delay as the tweak value (e.g., a metadata value) for a data block is calculated. In the embodiments herein, the encryption engine can include an independent metadata engine that determines the metadata value for a subsequent data block while the current data block is being encrypted.

    Programmable clock monitor
    7.
    发明授权
    Programmable clock monitor 有权

    公开(公告)号：US10379927B2

    公开(公告)日：2019-08-13

    申请号：US15340978

    申请日：2016-11-01

    Applicant: Xilinx, Inc.

    Inventor： Lester S. Sanders ,  Shravanthi Katam ,  Abhinaya Katta ,  Jayaram Pvss

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F1/12 ,  G06F1/08 ,  G06F11/30

    Abstract: An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.

    Memory utilization in a circuit design
    8.
    发明授权
    Memory utilization in a circuit design 有权

    公开(公告)号：US09792395B1

    公开(公告)日：2017-10-17

    申请号：US15013196

    申请日：2016-02-02

    Applicant: Xilinx, Inc.

    Inventor： Jayaram Pvss ,  Robert Bellarmin Susai ,  Khang K. Dao

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

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