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    Interface firewall for an integrated circuit of an expansion card
    1.
    发明授权
    Interface firewall for an integrated circuit of an expansion card 有权

    公开(公告)号：US10819680B1

    公开(公告)日：2020-10-27

    申请号：US15915981

    申请日：2018-03-08

    Applicant: Xilinx, Inc.

    Inventor： Sonal Santan ,  Umang Parekh ,  Jeffrey H. Seltzer ,  Khang K. Dao ,  Kyle Corbett

    IPC: H04L29/06 ,  G06F13/42

    Abstract: System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.

    Flexible data-driven software control of reconfigurable platforms
    6.
    发明授权
    Flexible data-driven software control of reconfigurable platforms 有权

    公开(公告)号：US11922223B1

    公开(公告)日：2024-03-05

    申请号：US17170427

    申请日：2021-02-08

    Applicant: Xilinx, Inc.

    Inventor： Adam P. Donlin ,  Kyle Corbett ,  Lizhi Hou ,  Julian M. Kain

    IPC: G06F9/50 ,  G06F9/38 ,  H04L9/06

    CPC classification number: G06F9/5077 ,  G06F9/3836 ,  G06F9/3877 ,  H04L9/0643

    Abstract: Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.

    Block-level code coverage in simulation of circuit designs
    8.
    发明授权
    Block-level code coverage in simulation of circuit designs 有权

    公开(公告)号：US09600613B1

    公开(公告)日：2017-03-21

    申请号：US14633417

    申请日：2015-02-27

    Applicant: Xilinx, Inc.

    Inventor： Kyle Corbett

    IPC: G06F17/50

    CPC classification number: G06F17/5022 ,  G06F17/5045 ,  G06F17/5054

    Abstract: Various example implementations are directed to methods and systems for simulating circuit designs having configuration parameters. According to one example implementation, code blocks of a circuit design for which execution of operations described by the code blocks is conditioned on a value of one or more of a set of configuration parameters, are identified. For each identified code block, a respective expression is determined that indicates whether or not the code block will be executed for different sets of values of the set of configuration parameters. The circuit design is simulated for a first set of values for the configuration parameters. The simulation is performed using a model that omits code blocks that describe sets of operations that will not be executed. The determined expressions are evaluated to determine whether or not each identified code block was realized in the simulation model.

    Debugging using tagged flip-flops
    9.
    发明授权
    Debugging using tagged flip-flops 有权
    使用标记的触发器进行调试

    公开(公告)号：US08813005B1

    公开(公告)日：2014-08-19

    申请号：US14016941

    申请日：2013-09-03

    Applicant: Xilinx, Inc.

    Inventor： Khang K. Dao ,  Kyle Corbett

    IPC: G06F17/50

    CPC classification number: G06F17/5022

    Abstract: Approaches for testing a module of a circuit design include tagging flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language specification of the module. In simulating with the netlist, event data are captured to a first file. A process determines whether or not event data in the first file matches event data in a second file of event data. In response to a difference determined between the first file and the second file, an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file is determined. The one of the plurality of flip-flops that output the first signal is determined, and the respective path name of the one flip-flop is output.

    Abstract translation: 用于测试电路设计的模块的方法包括：根据模块的硬件描述语言规范，将模块的网表中的触发器标记为具有触发器的相应路径名称的网表。 在与网表模拟时，将事件数据捕获到第一个文件。 进程确定第一文件中的事件数据是否匹配事件数据的第二文件中的事件数据。 响应于在第一文件和第二文件之间确定的差异，第一文件中最早出现的事件具有与第二文件中的相应事件的相关信号值不匹配的第一信号的相关信号值 决心，决意，决定。 确定输出第一信号的多个触发器中的一个，并输出一个触发器的相应路径名。

    Generation of a replay module for simulation of a circuit design
    10.
    发明授权
    Generation of a replay module for simulation of a circuit design 有权
    生成用于模拟电路设计的重放模块

    公开(公告)号：US08775987B1

    公开(公告)日：2014-07-08

    申请号：US13946137

    申请日：2013-07-19

    Applicant: Xilinx, Inc.

    Inventor： Adam P. Donlin ,  Kyle Corbett

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F17/5045 ,  G06F2217/02 ,  G06F2217/66

    Abstract: Approaches are disclosed for testing a module of a circuit design. The module is simulated a first time using a testbench on a programmed processor. Event data is captured to a first file during the simulating. For each event, the event data describes a signal identifier, an associated signal value, and an associated timestamp. The event data of the first file is transformed into a hardware description language (HDL) replay module.

    Abstract translation: 公开了用于测试电路设计的模块的方法。 首先使用编程处理器上的测试台模拟模块。 在模拟期间，事件数据被捕获到第一个文件。 对于每个事件，事件数据描述信号标识符，相关联的信号值和相关联的时间戳。 第一个文件的事件数据被转换成硬件描述语言（HDL）重放模块。

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