公开(公告)号：US20240222354A1

公开(公告)日：2024-07-04

申请号：US18091607

申请日：2022-12-30

Applicant: XILINX, INC.

Inventor： Narendra Kumar PULIPATI ,  Sree Rama Krishna Chaithnya SARASWATULA ,  Santosh YACHARENI ,  Anil Kumar KANDALA ,  Shidong ZHOU

IPC: H01L27/01 ,  G05F1/567 ,  G05F1/575 ,  H01L21/82 ,  H01L27/088 ,  H01L29/788

CPC classification number: H01L27/016 ,  G05F1/567 ,  G05F1/575 ,  H01L21/82 ,  H01L27/088 ,  H01L29/7881

Abstract: Techniques to utilize thin-oxide devices, such as gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs), in high voltage environments, such as to provide a high-voltage based low-power, temperature dependent, thin-oxide-only on-chip high current low drop out (LDO) regulator in a system-on-chip (SoC), such as provide power to configuration random-access memory (CRAM) cells distributed throughout configurable/programmable circuitry. Thin-oxide only circuitry may include thin-oxide-only amplifier circuitry, thin-oxide-only power gate circuitry, thin-oxide-only level shifters that shift voltage swings of control signals to voltage domains of the power gate circuitry, and thin-oxide-only clamp circuitry.

公开(公告)号：US20240353879A1

公开(公告)日：2024-10-24

申请号：US18137387

申请日：2023-04-20

Applicant: XILINX, INC.

Inventor： Lakshmi Venkata Satya Lalitha Indumathi JANASWAMY ,  Sree Rama Krishna Chaithnya SARASWATULA ,  Santosh YACHARENI ,  Anil Kumar KANDALA ,  Narendra Kumar PULIPATI ,  Shidong ZHOU

IPC: G05F1/46 ,  G05F1/56

CPC classification number: G05F1/465 ,  G05F1/562

Abstract: A cascaded thin-oxide N-Well voltage steering circuit includes a reference voltage generator that outputs a reference voltage within a range of first and second supply voltages, a first voltage steering circuit that outputs a higher available one of the reference voltage and the second supply voltage as an interim voltage, and a second voltage steering circuit that outputs a higher available one of the first voltage and the interim voltage at an output of the second voltage steering circuit. The interim voltage is applied to N-wells of PMOS transistors of the first voltage steering circuit. The output of the second voltage steering circuit is applied to N-wells of PMOS transistors of the second voltage steering circuit. The output of the second voltage steering circuit may also be applied to N-wells of PMOS transistors of other circuitry. The cascaded thin-oxide N-Well voltage steering circuit may consist substantially of thin-oxide PMOS transistors.

公开(公告)号：US20250061926A1

公开(公告)日：2025-02-20

申请号：US18235739

申请日：2023-08-18

Applicant: XILINX, INC.

Inventor： Santosh YACHARENI ,  Sree Rama Krishna Chaithnya SARASWATULA ,  Shidong ZHOU ,  Anil Kumar KANDALA ,  Narendra Kumar PULIPATI

IPC: G11C7/08 ,  G11C7/10 ,  G11C7/20

Abstract: Memory driver circuitry for driving a memory cell or cells of a memory device includes first driver path circuitry and selection circuitry. The first driver path circuitry includes driver circuitry that outputs a first signal and selection circuitry that receives the first signal and a second signal, and outputs a first selected signal. The first selected signal is a selected one of the first signal and the second signal. The selection circuitry of the memory driver circuitry receives a third signal and a fourth signal, and outputs a bias voltage signal to header circuitry of a memory cell. The bias voltage signal is a selected one of the third signal and the fourth signal. The third signal corresponds to the first selected signal.

公开(公告)号：US20250047285A1

公开(公告)日：2025-02-06

申请号：US18229152

申请日：2023-08-01

Applicant: XILINX, INC.

Inventor： Lakshmi Venkata Satya Lalitha Indumathi JANASWAMY ,  Narendra Kumar PULIPATI ,  Shidong ZHOU ,  Anil Kumar KANDALA ,  Santosh YACHARENI ,  Sree Rama Krishna Chaithnya SARASWATULA

IPC: H03K19/0185 ,  H03K3/037

Abstract: A level shifter may include a first transistor stack including at least four transistors arranged from a first voltage source to ground, including second and third transistors coupled with bias voltage source, and a fourth transistor coupled with an input to receive an input signal at a second voltage or ground. The level shifter may include a second transistor stack comprising at least four transistors arranged from the first voltage source to ground, including second and third transistors coupled with the bias voltage source, and a fourth transistor to receive an inverse of the input signal. A first transistor of the first transistor stack is cross-coupled with a first transistor of the second transistor stack. A level shifter may include a first output coupled with the second transistor stack between the second and third transistors to provide a first output signal at the first voltage or ground.