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公开(公告)号：US09857619B2
公开(公告)日：2018-01-02
申请号：US15009547
申请日：2016-01-28
Inventor： Yafeng Li , Xiangyi Peng
IPC: H01L27/14 , G02F1/1335 , G02F1/1339 , G02F1/1362 , G02F1/1368
CPC classification number: G02F1/133512 , G02F1/133514 , G02F1/13394 , G02F1/136259 , G02F1/136286 , G02F1/1368 , G02F2001/136295
Abstract: The present disclosure discloses a display panel, including a color filter plate substrate and an array substrate; the color filter plate substrate includes a black matrix and a protective layer; the color filter plate substrate and the array substrate are disposed opposite; the protective layer is disposed on a side of the black matrix oriented to the array substrate in a laser incidence region during laser repair. The protective layer is disposed on a side of the black matrix oriented to the array substrate in a laser incidence region during laser repair according to the disclosure, therefore, the preventive layer can protect the black matrix during laser repair from forming a through-hole on the black matrix that can leak light.
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公开(公告)号：US20170255308A1
公开(公告)日：2017-09-07
申请号：US14912601
申请日：2016-01-29
Inventor： Yafeng Li , Xiangyi Peng
IPC: G06F3/041 , G02F1/1335 , G02F1/1339 , G02F1/1362 , G02F1/1343 , G02F1/1333 , G02F1/1368
CPC classification number: G06F3/0412 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133514 , G02F1/13394 , G02F1/134309 , G02F1/134363 , G02F1/13439 , G02F1/136209 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2001/133357 , G02F2001/13396 , G02F2001/13398 , G02F2201/121 , G02F2201/123 , G02F2201/40 , G02F2202/104 , G06F3/044
Abstract: The present invention provides an in-cell touch display panel. In the in-cell touch display panel of the present invention, a first planarization layer (14) is solely arranged between a pixel electrode (15) and source/drain electrodes (45) located on one side of a TFT substrate (1) and the pixel electrode (15) is connected through a second via (141) formed in the first planarization layer (14) to the source/drain electrodes (45) so that compared to the prior art, the thickness of two passivation layers is omitted between the pixel electrode (15) and the source/drain electrodes (45) and negative influence caused by overlapping of vias between the first passivation layer (16) and the first planarization layer (14) and between the second passivation layer (18) and the first planarization layer (14) can be eliminated, whereby there is no need to take into consideration the relationship of the first planarization layer with respect to the first passivation layer and the second passivation layer in making a design so that the aperture ratio of the pixel can be greatly increased. Further, since the number of vias formed is reduced, the structure is simple and the manufacturing difficulty is lowered down to thereby improve product yield.
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公开(公告)号：US10126343B2
公开(公告)日：2018-11-13
申请号：US14912924
申请日：2016-01-29
Inventor： Yafeng Li , Xiangyi Peng
IPC: G01R31/00 , G01R31/08 , G02F1/1362 , G02F1/1368 , G09G3/00 , G02F1/1333 , G09G3/36
Abstract: The invention provides an ESD detection method for array substrate. By connecting the first metal layer on array substrate through the first wire to the first test point, connecting the second metal layer on array substrate through the second wire to the second test point, when ESD occurs on array substrate, the resistance detection device is used to measure the resistance between the first and second test points. If the resistance is positive infinity, ESD did not occur between the first and second metal layers; if the resistance is within a measurable range, ESD occurs between the first and second metal layers. The resistance is used to locate the location of ESD occurrence on array substrate. Compared to known method using microscope to search ESD location, the invention can locate ESD location on array substrate more accurately and rapidly to save time and labor as well as detection cost.
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Patent Agency Ranking
公开(公告)号：US20180033712A1
公开(公告)日：2018-02-01
申请号：US14914655
申请日：2016-01-28
Inventor： Yafeng Li , Xiangyi Peng
IPC: H01L23/34 , H01L29/786 , H01L27/12
CPC classification number: H01L23/345 , G02F1/133382 , G02F1/136209 , G02F1/1368 , G02F2202/104 , H01L27/1222 , H01L27/124 , H01L27/1255 , H01L29/78633 , H01L29/78672
Abstract: The invention provides an array substrate and activation method for TFT elements in the array substrate. The array substrate comprises a shielding metal layer (10) and a TFT layer (20) disposed on the shielding metal layer (10); by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) to accelerate activating the TFT elements in the TFT layer (20). The activation method, by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) before activating the TFT elements in the TFT layer (20), accelerates activating the TFT elements in the TFT layer (20). The method is applicable to activating the TFT elements in array substrate in low temperature environment.
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公开(公告)号：US10156756B2
公开(公告)日：2018-12-18
申请号：US14907865
申请日：2016-01-12
Inventor： Yafeng Li , Xiangyi Peng
IPC: G02F1/1343
Abstract: A liquid crystal panel and a pixel structure thereof are described. The pixel structure has a common electrode, a protecting layer, a plurality of pixel electrodes, and a plurality of first channels. The protecting layer is located on the common electrode; the pixel electrodes are located on the protecting layer; and the first channels are located between the neighboring pixel electrodes and pass through the protecting layer, so that the first channels expose a top surface of the common electrode.
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公开(公告)号：US20180031623A1
公开(公告)日：2018-02-01
申请号：US14912924
申请日：2016-01-29
Inventor： Yafeng Li , Xiangyi Peng
IPC: G01R31/00 , G02F1/1368 , G01R31/08 , G02F1/1362
CPC classification number: G01R31/001 , G01R31/08 , G02F1/133345 , G02F1/136204 , G02F1/136286 , G02F1/1368 , G02F2001/136254 , G02F2001/136295 , G02F2202/104 , G09G3/006 , G09G3/3648 , G09G2300/0417
Abstract: The invention provides an ESD detection method for array substrate. By connecting the first metal layer on array substrate through the first wire to the first test point, connecting the second metal layer on array substrate through the second wire to the second test point, when ESD occurs on array substrate, the resistance detection device is used to measure the resistance between the first and second test points. If the resistance is positive infinity, ESD did not occur between the first and second metal layers; if the resistance is within a measurable range, ESD occurs between the first and second metal layers. The resistance is used to locate the location of ESD occurrence on array substrate. Compared to known method using microscope to search ESD location, the invention can locate ESD location on array substrate more accurately and rapidly to save time and labor as well as detection cost.
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公开(公告)号：US09921673B2
公开(公告)日：2018-03-20
申请号：US14912601
申请日：2016-01-29
Inventor： Yafeng Li , Xiangyi Peng
IPC: G02F1/1333 , G06F3/041 , G02F1/1335 , G02F1/1368 , G02F1/1362 , G02F1/1343 , G02F1/1339
CPC classification number: G06F3/0412 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133514 , G02F1/13394 , G02F1/134309 , G02F1/134363 , G02F1/13439 , G02F1/136209 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2001/133357 , G02F2001/13396 , G02F2001/13398 , G02F2201/121 , G02F2201/123 , G02F2201/40 , G02F2202/104 , G06F3/044
Abstract: The present invention provides an in-cell touch display panel. In the in-cell touch display panel of the present invention, a first planarization layer (14) is solely arranged between a pixel electrode (15) and source/drain electrodes (45) located on one side of a TFT substrate (1) and the pixel electrode (15) is connected through a second via (141) formed in the first planarization layer (14) to the source/drain electrodes (45) so that compared to the prior art, the thickness of two passivation layers is omitted between the pixel electrode (15) and the source/drain electrodes (45) and negative influence caused by overlapping of vias between the first passivation layer (16) and the first planarization layer (14) and between the second passivation layer (18) and the first planarization layer (14) can be eliminated, whereby there is no need to take into consideration the relationship of the first planarization layer with respect to the first passivation layer and the second passivation layer in making a design so that the aperture ratio of the pixel can be greatly increased. Further, since the number of vias formed is reduced, the structure is simple and the manufacturing difficulty is lowered down to thereby improve product yield.
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公开(公告)号：US09905493B2
公开(公告)日：2018-02-27
申请号：US14914655
申请日：2016-01-28
Inventor： Yafeng Li , Xiangyi Peng
IPC: G02F1/133 , H01L23/34 , H01L27/12 , H01L29/786 , G02F1/1362 , G02F1/1368 , G02F1/1333
CPC classification number: H01L23/345 , G02F1/133382 , G02F1/136209 , G02F1/1368 , G02F2202/104 , H01L27/1222 , H01L27/124 , H01L27/1255 , H01L29/78633 , H01L29/78672
Abstract: The invention provides an array substrate and activation method for TFT elements in the array substrate. The array substrate comprises a shielding metal layer (10) and a TFT layer (20) disposed on the shielding metal layer (10); by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) to accelerate activating the TFT elements in the TFT layer (20). The activation method, by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) before activating the TFT elements in the TFT layer (20), accelerates activating the TFT elements in the TFT layer (20). The method is applicable to activating the TFT elements in array substrate in low temperature environment.
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