公开(公告)号：US20080186757A1

公开(公告)日：2008-08-07

申请号：US11743453

申请日：2007-05-02

申请人： Wen-Chin Lin ,  Hsu-Chen Cheng ,  Yu-Jen Wang ,  Denny Tang

发明人： Wen-Chin Lin ,  Hsu-Chen Cheng ,  Yu-Jen Wang ,  Denny Tang

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/005 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.

摘要翻译： 这里公开了一种用于创建用于构建存储器集成电路芯片的高级MRAM阵列的技术。 更具体地，所公开的原理提供了由高速磁存储器单元的阵列中的至少一个和高密度磁存储单元阵列中的至少一个的组合构成的集成电路存储器芯片。 因此，如本文所公开的构造的存储器芯片提供了在相同存储器芯片上的高速和高密度存储器单元的益处。 结果，受益于使用（或甚至需要的）高速存储器单元的应用由高速存储单元阵列中的存储单元提供。

公开(公告)号：US07719882B2

公开(公告)日：2010-05-18

申请号：US11743453

申请日：2007-05-02

申请人： Wen-Chin Lin ,  Hsu-Chen Cheng ,  Yu-Jen Wang ,  Denny Tang

发明人： Wen-Chin Lin ,  Hsu-Chen Cheng ,  Yu-Jen Wang ,  Denny Tang

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/005 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.

摘要翻译： 这里公开了一种用于创建用于构建存储器集成电路芯片的高级MRAM阵列的技术。 更具体地，所公开的原理提供了由高速磁存储器单元的阵列中的至少一个和高密度磁存储单元的阵列中的至少一个的组合构成的集成电路存储器芯片。 因此，如本文所公开的构造的存储器芯片提供了在相同存储器芯片上的高速和高密度存储器单元的益处。 结果，受益于使用（或甚至需要的）高速存储器单元的应用由高速存储单元阵列中的存储单元提供。

公开(公告)号：US07312506B2

公开(公告)日：2007-12-25

申请号：US11093652

申请日：2005-03-30

申请人： Yu-Jen Wang ,  Chih-Huang Lai ,  Denny Tang ,  Wen Chin Lin

发明人： Yu-Jen Wang ,  Chih-Huang Lai ,  Denny Tang ,  Wen Chin Lin

IPC分类号： H01L29/82

CPC分类号： G11C11/16

摘要： A memory cell structure. A first conductive line is cladded by at least two first ferromagnetic layers respectively having a first easy axis and a second easy axis, a nano oxide layer located between the first ferromagnetic layers, and a first pinned ferromagnetic layer. The first and second easy axes are 90 degree twisted-coupled with the first easy axis parallel to the length of the first conductive line and the second easy axis perpendicular to the length of the first conductive line. A storage device is adjacent to the first conductive line, receiving a magnetic field generated from a current flowing through the first conductive line.

摘要翻译： 存储单元结构。 第一导线由分别具有第一容易轴和第二容易轴的至少两个第一铁磁层，位于第一铁磁层之间的纳米氧化物层和第一固定铁磁层包层。 第一和第二容易轴与第一容易轴90度扭转耦合，平行于第一导电线的长度，第二容易轴垂直于第一导线的长度。 存储装置与第一导线相邻，接收从流经第一导线的电流产生的磁场。

公开(公告)号：US07443638B2

公开(公告)日：2008-10-28

申请号：US10907974

申请日：2005-04-22

申请人： Yu-Jen Wang ,  Chih-Huang Lai ,  Wen-Chin Lin ,  Denny Tang ,  Chao-Hsiung Wang

发明人： Yu-Jen Wang ,  Chih-Huang Lai ,  Wen-Chin Lin ,  Denny Tang ,  Chao-Hsiung Wang

IPC分类号： G11B5/39 ,  G11B5/33

CPC分类号： G11B5/3929 ,  B82Y10/00 ,  G11B2005/3996

摘要： Disclosed herein is a magnetoresistive structure, for example useful as a spin-valve or GMR stack in a magnetic sensor, and a fabrication method thereof. The magnetoresistive structure uses twisted coupling to induce a perpendicular magnetization alignment between the free layer and the pinned layer. Ferromagnetic layers of the free and pinned layers are exchange-coupled using antiferromagnetic layers having substantially parallel exchange-biasing directions. Thus, embodiments can be realized that have antiferromagnetic layers formed of a same material and/or having a same blocking temperature. At least one of the free and pinned layers further includes a second ferromagnetic layer and an insulating layer, such as a NOL, between the two ferromagnetic layers. The insulating layer causes twisted coupling between the two ferromagnetic layers, rotating the magnetization direction of one 90 degrees relative to the magnetization direction of the other.

摘要翻译： 这里公开了一种例如在磁传感器中用作自旋阀或GMR堆叠的磁阻结构及其制造方法。 磁阻结构使用扭转耦合来引起自由层和被钉扎层之间的垂直磁化对准。 使用具有基本平行的交换偏压方向的反铁磁层来交换耦合自由和被钉扎层的铁磁层。 因此，可以实现具有由相同材料形成的反铁磁层和/或具有相同阻挡温度的实施例。 自由和被钉扎层中的至少一个还包括在两个铁磁层之间的第二铁磁层和绝缘层，例如NOL。 绝缘层引起两个铁磁层之间的扭转耦合，使相对于另一个的磁化方向旋转90度的磁化方向。

公开(公告)号：US20060238925A1

公开(公告)日：2006-10-26

申请号：US10907974

申请日：2005-04-22

申请人： Yu-Jen Wang ,  Chih-Huang Lai ,  Wen-Chin Lin ,  Denny Tang ,  Chao-Hsiung Wang

发明人： Yu-Jen Wang ,  Chih-Huang Lai ,  Wen-Chin Lin ,  Denny Tang ,  Chao-Hsiung Wang

IPC分类号： G11B5/33 ,  G11B5/127

CPC分类号： G11B5/3929 ,  B82Y10/00 ,  G11B2005/3996

摘要： Disclosed herein is a magnetoresistive structure, for example useful as a spin-valve or GMR stack in a magnetic sensor, and a fabrication method thereof. The magnetoresistive structure uses twisted coupling to induce a perpendicular magnetization alignment between the free layer and the pinned layer. Ferromagnetic layers of the free and pinned layers are exchange-coupled using antiferromagnetic layers having substantially parallel exchange-biasing directions. Thus, embodiments can be realized that have antiferromagnetic layers formed of a same material and/or having a same blocking temperature. At least one of the free and pinned layers further includes a second ferromagnetic layer and an insulating layer, such as a NOL, between the two ferromagnetic layers. The insulating layer causes twisted coupling between the two ferromagnetic layers, rotating the magnetization direction of one 90 degrees relative to the magnetization direction of the other.

摘要翻译： 这里公开了一种例如在磁传感器中用作自旋阀或GMR堆叠的磁阻结构及其制造方法。 磁阻结构使用扭转耦合来引起自由层和被钉扎层之间的垂直磁化对准。 使用具有基本平行的交换偏压方向的反铁磁层来交换耦合自由和被钉扎层的铁磁层。 因此，可以实现具有由相同材料形成的反铁磁层和/或具有相同阻挡温度的实施例。 自由和被钉扎层中的至少一个还包括在两个铁磁层之间的第二铁磁层和绝缘层，例如NOL。 绝缘层引起两个铁磁层之间的扭转耦合，使相对于另一个的磁化方向旋转90度的磁化方向。

公开(公告)号：US07964900B2

公开(公告)日：2011-06-21

申请号：US12586688

申请日：2009-09-24

申请人： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/08

摘要： A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

摘要翻译： 半导体衬底包括在半导体子结构上形成的图案化硬掩模膜的开口下方的半绝缘部分，其厚度足以防止带电粒子通过硬掩模。 半绝缘部分包括带电粒子并且可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。 带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

公开(公告)号：US07622358B2

公开(公告)日：2009-11-24

申请号：US11241574

申请日：2005-09-30

申请人： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

IPC分类号： H01L21/76

CPC分类号： H01L21/76 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/08

摘要： A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

摘要翻译： 在半导体衬底中形成半绝缘部分的方法提供了将半导体衬底上的硬掩模膜沉积到足以防止带电粒子穿过硬掩模的厚度。 硬掩模被图案化以产生开孔，在注入过程中带电粒子通过该开口进入衬底。 半绝缘部分可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。 带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

公开(公告)号：US07599215B2

公开(公告)日：2009-10-06

申请号：US11840051

申请日：2007-08-16

申请人： Wen-Chin Lin ,  Denny Tang ,  Hsu Chen Cheng

发明人： Wen-Chin Lin ,  Denny Tang ,  Hsu Chen Cheng

IPC分类号： G11C11/15

CPC分类号： G11C11/16

摘要： Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.

摘要翻译： 这里公开了具有小角度切换写入线的触发模式磁阻随机存取存储器（MRAM）器件以及触发模式切换MRAM器件的相关方法。 还公开了根据所公开的原理构造的MRAM装置的布局。 一般来说，所公开的原理提供用于切换切换模式MRAM器件的非正交对准的触发模式写入线，其使用偏置场来降低切换每个器件的磁状态所需的阈值。 虽然常规的切换模式写入线提供所施加的磁场的期望的正交取向以优化器件切换，但偏置场的使用影响该正交取向。 如本文所公开的，通过非正交对准这两个写入线，可以补偿偏置场的有害影响，使得如所期望的那样，施加到两条线的器件的净场也基本正交。

公开(公告)号：US07573736B2

公开(公告)日：2009-08-11

申请号：US11752157

申请日：2007-05-22

申请人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/00

CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675

摘要： The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.

摘要翻译： 本公开提供了一种磁存储元件。 存储元件包括磁隧道结（MTJ）元件和电极。 电极包括钉扎层，钉扎层和非磁性导电层。 在一个实施例中，MTJ元件包括具有第一表面区域的第一表面，并且电极包括第二表面。 在该实施例中，电极的第二表面耦合到MTJ元件的第一表面，使得形成界面区域，并且界面面积小于第一表面积。

公开(公告)号：US20090290410A1

公开(公告)日：2009-11-26

申请号：US12537093

申请日：2009-08-06

申请人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

发明人： Yu-Jen Wang ,  Denny Tang ,  Hsu-Chen Cheng

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675

摘要： The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.

摘要翻译： 本公开提供了一种磁存储元件。 存储元件包括磁隧道结（MTJ）元件和电极。 电极包括钉扎层，钉扎层和非磁性导电层。 在一个实施例中，MTJ元件包括具有第一表面区域的第一表面，并且电极包括第二表面。 在该实施例中，电极的第二表面耦合到MTJ元件的第一表面，使得形成界面区域，并且界面面积小于第一表面积。