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    Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching
    1.
    发明申请
    Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching 有权
    氟植入物隔离电介质结构提高双极晶体管性能和匹配

    公开(公告)号：US20130065374A1

    公开(公告)日：2013-03-14

    申请号：US13451355

    申请日：2012-04-19

    申请人： Weidong Tian ,  Ming-Yeh Chuang ,  Rajni J. Aggarwal

    发明人： Weidong Tian ,  Ming-Yeh Chuang ,  Rajni J. Aggarwal

    IPC分类号： H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/1004 ,  H01L29/66272

    摘要： A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.

    摘要翻译： 一种制造包括双极晶体管的集成电路的方法，其降低了等离子体蚀刻期间由充电引起的晶体管性能下降和晶体管失配的影响，以及如此形成的集成电路。 在形成隔离电介质之前，在要形成基极和发射极之间的隔离电介质结构的那些位置处进行氟注入。 隔离电介质结构可以通过浅沟槽隔离来形成，其中氟注入在沟槽蚀刻之后进行，或LOCOS氧化，其中氟注入在热氧化之前进行。 氟注入可以垂直于器件表面或与法线成一定角度。 然后执行集成电路的完成，包括使用需要等离子体蚀刻的相对厚的铜金属化。

    Fluorine implant under isolation dielectric structures to improve bipolar transistor performance and matching
    2.
    发明授权
    Fluorine implant under isolation dielectric structures to improve bipolar transistor performance and matching 有权
    隔离介质结构中的氟植入物，以改善双极晶体管的性能和匹配

    公开(公告)号：US08609501B2

    公开(公告)日：2013-12-17

    申请号：US13451355

    申请日：2012-04-19

    申请人： Weidong Tian ,  Ming-Yeh Chuang ,  Rajni J. Aggarwal

    发明人： Weidong Tian ,  Ming-Yeh Chuang ,  Rajni J. Aggarwal

    IPC分类号： H01L21/331

    CPC分类号： H01L29/732 ,  H01L29/1004 ,  H01L29/66272

    摘要： A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.

    摘要翻译： 一种制造包括双极晶体管的集成电路的方法，其降低了等离子体蚀刻期间由充电引起的晶体管性能下降和晶体管失配的影响，以及如此形成的集成电路。 在形成隔离电介质之前，在要形成基极和发射极之间的隔离电介质结构的那些位置处进行氟注入。 隔离电介质结构可以通过浅沟槽隔离来形成，其中氟注入在沟槽蚀刻之后进行，或LOCOS氧化，其中氟注入在热氧化之前进行。 氟注入可以垂直于器件表面或与法线成一定角度。 然后执行集成电路的完成，包括使用需要等离子体蚀刻的相对厚的铜金属化。

    High Sheet Resistor in CMOS Flow
    3.
    发明申请
    High Sheet Resistor in CMOS Flow 有权
    CMOS流程中的高片电阻

    公开(公告)号：US20120098071A1

    公开(公告)日：2012-04-26

    申请号：US13278595

    申请日：2011-10-21

    申请人： Rajni J. Aggarwal ,  Jau-Yuann Yang

    发明人： Rajni J. Aggarwal ,  Jau-Yuann Yang

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L28/20 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/283 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/4916 ,  H01L29/66583 ,  H01L29/6659

    摘要： An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

    摘要翻译： 一种包含CMOS栅极和反向多晶硅栅极材料电阻器的集成电路，其具有与CMOS栅极的NMOS晶体管的NSD层同时注入并与CMOS栅极的PMOS晶体管的PSD层同时注入的体区，以及 在主体区域上具有与CMOS栅极上的侧壁间隔物分开的材料形成的电阻器硅化物阻挡层。 形成包含CMOS栅极的集成电路和反向掺杂的多晶硅栅极材料电阻器的过程，其将CMOS电极的NMOS晶体管的NSD层同时与电阻体的主体区域并入，并且与PMOS晶体管的PSD层同时 CMOS栅极，并且在与CMOS栅极上的侧壁间隔物分离的材料的主体区域上形成电阻器硅化物阻挡层。

    Electrical test structure to detect stress induced defects using diodes
    6.
    发明授权
    Electrical test structure to detect stress induced defects using diodes 有权
    使用二极管检测应力诱发缺陷的电气测试结构

    公开(公告)号：US07968878B2

    公开(公告)日：2011-06-28

    申请号：US12537685

    申请日：2009-08-07

    申请人： Rajni J. Aggarwal ,  YuGuo Wang

    发明人： Rajni J. Aggarwal ,  YuGuo Wang

    IPC分类号： H01L29/10 ,  H01L21/66

    CPC分类号： H01L27/0629 ,  H01L22/34 ,  H01L27/0814 ,  H01L2924/3011

    摘要： A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects.

    摘要翻译： 公开了用于监测应力诱发缺陷的蛇形双门控二极管阵列。 二极管阵列配置有邻近有效区域的相邻栅极段和栅极环路，以最大化对应力引起的缺陷的敏感性。 二极管阵列与常规电气测试兼容。 扫描电容显微镜（SCM）和扫描扩散电阻显微镜（SSRM）可用于分离各种应力诱发的缺陷。 栅极配置的变化允许估计电路布局对形成应力诱发缺陷的影响。

    Drawn Dummy FeCAP, Via and Metal Structures
    10.
    发明申请
    Drawn Dummy FeCAP, Via and Metal Structures 有权
    绘制虚拟FeCAP，通孔和金属结构

    公开(公告)号：US20100090340A1

    公开(公告)日：2010-04-15

    申请号：US12576340

    申请日：2009-10-09

    申请人： Scott R. Summerfelt ,  Rajni J. Aggarwal

    发明人： Scott R. Summerfelt ,  Rajni J. Aggarwal

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L23/522 ,  H01L23/5223 ,  H01L23/585 ,  H01L27/0207 ,  H01L27/11507 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

    摘要： An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.

    摘要翻译： 一种集成电路，其包含配置在线性或矩形阵列中并且对称地位于集成电路中的部件上的氢可渗透虚设通孔。 包含具有相同布局的匹配部件和在匹配部件上具有相同配置的氢可渗透虚拟过孔的集成电路。 形成集成电路的过程，该集成电路包含具有相同布局的匹配部件和在匹配部件上具有相同构造的氢可渗透虚设通孔。