公开(公告)号：US08108760B2

公开(公告)日：2012-01-31

申请号：US12503607

申请日：2009-07-15

Applicant: Warren J. Gross ,  Shie Mannor ,  Gabi Sarkis

Inventor： Warren J. Gross ,  Shie Mannor ,  Gabi Sarkis

IPC: H03M13/00

CPC classification number: H03M13/1171 ,  H04L1/0057

Abstract: A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code. Using the logic circuitry each probability message is passed through the factor graph by performing for each received symbol at the variable nodes the equality function, at the permutation nodes one of multiplication and division, and at the parity check nodes the parity check function, wherein each of the variable nodes provides an output symbol in dependence upon each received symbol.

Abstract translation: 提供了一种具有包括伽罗瓦域元素的奇偶校验矩阵的线性码随机解码的解码方法和系统。 一组编码样本的每个编码样本首先按照与编码样本集合的噪声电平成比例的缩放因子来缩放。 然后将每个经缩放的编码样本转换成相应的概率。 对于每个概率，相应的概率消息是通过将每个概率编码为符号或比特的序列而生成的。 然后将每个概率消息提供给用于随机解码的逻辑电路的相应可变节点。 逻辑电路表示线性码的奇偶校验矩阵的因子图。 使用逻辑电路，通过对可变节点处的每个接收到的符号执行相等函数，在置换节点乘法和除法之一以及奇偶校验节点处执行奇偶校验功能，将每个概率消息传递通过因子图，其中每个 可变节点根据每个接收的符号提供输出符号。

公开(公告)号：US08095860B2

公开(公告)日：2012-01-10

申请号：US12153749

申请日：2008-05-23

Applicant: Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

Inventor： Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

IPC: H03M13/00

CPC classification number: H03M13/1102

Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.

Abstract translation: 本发明涉及一种具有奇偶校验矩阵的线性块码随机解码的解码方法和系统。 一组编码样本的每个编码样本被转换成相应的概率。 对于每个概率，相应的概率消息是通过将每个概率编码为数字符号序列而生成的。 然后将每个概率消息提供给用于随机解码的逻辑电路的相应节点。 逻辑电路表示线性块码的奇偶校验矩阵的因子图。 使用逻辑电路处理每个概率消息以确定信息符号的估计序列。 如果等式节点处于保持状态，则从相应的存储器提供所选择的符号，相应的存储器当相同处于保持状态以外的状态时，通过存储来自等式节点的输出符号来更新。

公开(公告)号：US20080256343A1

公开(公告)日：2008-10-16

申请号：US12081155

申请日：2008-04-11

Applicant: Warren J. Gross ,  Shie Mannor

Inventor： Warren J. Gross ,  Shie Mannor

IPC: H01R13/60 ,  H03K19/003

CPC classification number: G05B19/045

Abstract: A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic gates switching activity of a plurality of the logic gates is sensed to determine switching data indicative of a total switching activity of the plurality of the logic gates. The iterative process is iterated using the logic circuitry until convergence is indicated by the switching data. Similarly, a scaling factor for use in decoding processes is determined based on the switching data.

Abstract translation: 提供了一种用于确定迭代过程的收敛并基于逻辑电路的切换活动来估计解码过程中的缩放因子的方法和系统。 在使用包括逻辑门的逻辑电路的迭代处理的执行期间，检测多个逻辑门的切换活动，以确定指示多个逻辑门的总切换活动的切换数据。 使用逻辑电路迭代迭代过程，直到收敛由切换数据指示。 类似地，基于切换数据确定用于解码处理的缩放因子。

公开(公告)号：US20080294970A1

公开(公告)日：2008-11-27

申请号：US12153749

申请日：2008-05-23

Applicant: Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

Inventor： Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

IPC: G06F11/00

CPC classification number: H03M13/1102

Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.

Abstract translation: 本发明涉及一种具有奇偶校验矩阵的线性块码随机解码的解码方法和系统。 一组编码样本的每个编码样本被转换成相应的概率。 对于每个概率，相应的概率消息是通过将每个概率编码为数字符号序列而生成的。 然后将每个概率消息提供给用于随机解码的逻辑电路的相应节点。 逻辑电路表示线性块码的奇偶校验矩阵的因子图。 使用逻辑电路处理每个概率消息以确定信息符号的估计序列。 如果等式节点处于保持状态，则从相应的存储器提供所选择的符号，相应的存储器当相同处于保持状态以外的状态时，通过存储来自等式节点的输出符号来更新。

公开(公告)号：US09100153B2

公开(公告)日：2015-08-04

申请号：US13150971

申请日：2011-06-01

Applicant: Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

Inventor： Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

IPC: H04L1/00

CPC classification number: H04L1/005

Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided. A plurality of sub nodes forms a variable node for performing an equality function in an iterative decoding process. Internal memory is interposed between the sub nodes such that the internal memory is connected to an output port of a respective sub node and to an input port of a following sub node, the internal memory for providing a chosen symbol if a respective sub node is in a hold state, and wherein at least two sub nodes share a same internal memory.

Abstract translation: 提供了一种用于对从传输信道接收的一组编码样本进行迭代解码的方法。 接收表示传输信道的噪声电平的数据信号。 然后根据数据信号确定缩放因子，并使用缩放因子对编码的样本进行缩放。 然后对经缩放的编码样本进行迭代解码。 此外，提供了一种用于初始化边缘存储器的方法。 在初始化阶段期间，从逻辑电路的一个节点接收初始化符号并存储在相应的边缘存储器中。 当接收到的符号占据边缘存储器的预定部分时，终止初始化阶段。 使用存储从边缘存储器中的节点接收的输出符号的逻辑电路来执行迭代处理，并且从边缘存储器检索符号并将其提供为节点的输出符号。 还提供了一种用于高度可变节点的架构。 多个子节点形成用于在迭代解码处理中执行相等函数的变量节点。 内部存储器插入在子节点之间，使得内部存储器连接到相应子节点的输出端口和连接到后续子节点的输入端口，内部存储器用于在各个子节点处于 保持状态，并且其中至少两个子节点共享相同的内部存储器。

公开(公告)号：US08108758B2

公开(公告)日：2012-01-31

申请号：US11902410

申请日：2007-09-21

Applicant: Warren J. Gross ,  Shie Mannor

Inventor： Warren J. Gross ,  Shie Mannor

IPC: H03M13/45

CPC classification number: H03M13/1137 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1191 ,  H03M13/1194 ,  H03M13/19 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3753 ,  H03M13/658

Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.

Abstract translation: 本发明涉及一种用于LDPC码随机解码的解码方法和系统。 一组编码样本的每个编码样本首先按照与编码样本集合的噪声电平成比例的缩放因子来缩放。 然后将每个经缩放的编码样本转换成相应的概率。 对于每个概率，相应的概率消息是通过将每个概率编码为数字比特序列而生成的。 然后将每个概率消息提供给用于随机解码的逻辑电路的相应节点。 逻辑电路表示LDPC码的奇偶校验矩阵的因子图。 使用逻辑电路，每个概率消息被处理以确定信息比特的估计序列。 如果等式节点处于保持状态，则从相应的边缘存储器提供所选择的位，当对应的边缘存储器处于除保持状态之外的状态时，通过存储来自等式节点的输出位来更新。

公开(公告)号：US20110293045A1

公开(公告)日：2011-12-01

申请号：US13150971

申请日：2011-06-01

Applicant: Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

Inventor： Warren J. Gross ,  Shie Mannor ,  Saeed Sharifi Tehrani

IPC: H04L27/06 ,  H04L27/00

CPC classification number: H04L1/005

Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided. A plurality of sub nodes forms a variable node for performing an equality function in an iterative decoding process. Internal memory is interposed between the sub nodes such that the internal memory is connected to an output port of a respective sub node and to an input port of a following sub node, the internal memory for providing a chosen symbol if a respective sub node is in a hold state, and wherein at least two sub nodes share a same internal memory.

Abstract translation: 提供了一种用于对从传输信道接收的一组编码样本进行迭代解码的方法。 接收表示传输信道的噪声电平的数据信号。 然后根据数据信号确定缩放因子，并使用缩放因子对编码的样本进行缩放。 然后对经缩放的编码样本进行迭代解码。 此外，提供了一种用于初始化边缘存储器的方法。 在初始化阶段期间，从逻辑电路的一个节点接收初始化符号并存储在相应的边缘存储器中。 当接收到的符号占据边缘存储器的预定部分时，终止初始化阶段。 使用存储从边缘存储器中的节点接收的输出符号的逻辑电路来执行迭代处理，并且从边缘存储器检索符号并将其提供为节点的输出符号。 还提供了一种用于高度可变节点的架构。 多个子节点形成用于在迭代解码处理中执行相等函数的变量节点。 内部存储器插入在子节点之间，使得内部存储器连接到相应子节点的输出端口和连接到后续子节点的输入端口，内部存储器用于在各个子节点处于 保持状态，并且其中至少两个子节点共享相同的内部存储器。

公开(公告)号：US20120054576A1

公开(公告)日：2012-03-01

申请号：US13216373

申请日：2011-08-24

Applicant: Warren Gross ,  Saied Hemati ,  Shie Mannor ,  Ali Naderi ,  Francois Leduc-Primeau

Inventor： Warren Gross ,  Saied Hemati ,  Shie Mannor ,  Ali Naderi ,  Francois Leduc-Primeau

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/6544 ,  H03M13/1117 ,  H03M13/1137 ,  H03M13/1142 ,  H03M13/1151 ,  H03M13/3707 ,  H03M13/6575 ,  H03M13/6577

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails.

Abstract translation: 低密度奇偶校验（LDPC）码在接近链路信道容量的速率下提供误码校正，并且在存在数据破坏噪声的带宽或返回信道受限链路上进行可靠和有效的信息传输。 它们还提供了在代码长度，线性处理复杂度以及与代码长度相关联的并行性方面，指数速度接近通道容量的性能。 它们还提供与解码复杂性和错误底层限制可实现的误码率有关的挑战。 因此，具有降低的复杂性，降低的功耗和改进的性能的编码器被公开，其具有各种改进，包括简化通过传递消息，其中脉冲宽度被调制与相应的消息幅度相关联的通信，延迟根据变量节点状态的检查操作， 解码器多次具有用于恒定信道值集合的不同随机数发生器种子，并且当第一解码器的尝试失败时，采用具有随机化分量的第二解码器。

公开(公告)号：US20080077839A1

公开(公告)日：2008-03-27

申请号：US11902410

申请日：2007-09-21

Applicant: Warren Gross ,  Shie Mannor

Inventor： Warren Gross ,  Shie Mannor

IPC: G06F11/10

CPC classification number: H03M13/1137 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1191 ,  H03M13/1194 ,  H03M13/19 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3753 ,  H03M13/658

Abstract: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.

Abstract translation: 本发明涉及一种用于LDPC码随机解码的解码方法和系统。 一组编码样本的每个编码样本首先按照与编码样本集合的噪声电平成比例的缩放因子来缩放。 然后将每个经缩放的编码样本转换成相应的概率。 对于每个概率，相应的概率消息是通过将每个概率编码为数字比特序列而生成的。 然后将每个概率消息提供给用于随机解码的逻辑电路的相应节点。 逻辑电路表示LDPC码的奇偶校验矩阵的因子图。 使用逻辑电路，每个概率消息被处理以确定信息比特的估计序列。 如果等式节点处于保持状态，则从相应的边缘存储器提供所选择的位，当对应的边缘存储器处于除保持状态之外的状态时，通过存储来自等式节点的输出位来更新。

公开(公告)号：US08898537B2

公开(公告)日：2014-11-25

申请号：US13050065

申请日：2011-03-17

Applicant: Warren Gross ,  Francois Leduc-Primeau ,  Saied Hemati ,  Shie Mannor

Inventor： Warren Gross ,  Francois Leduc-Primeau ,  Saied Hemati ,  Shie Mannor

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/25

CPC classification number: H03M13/255 ,  H03M13/1111 ,  H03M13/1125 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1165 ,  H03M13/6544 ,  H03M13/658 ,  H03M13/6597

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. LDPC codes also offer error correction performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with the code length. They also offer challenges relating to the decoding complexity of the binary error-correction codes themselves and error floors limiting achievable bit-error rates. A new Relaxed Half-Stochastic (RHS) decoding algorithm is presented that reduces decoding complexity for high decoding throughput applications. The RHS algorithm uses an approach based on stochastic decoding algorithms but differs significantly from the conventional approaches of LDPC decoder implementation. The RHS algorithm also leads to a randomized decoding technique called redecoding that addresses the error floor limitation.

Abstract translation: 低密度奇偶校验（LDPC）码在接近链路信道容量的速率下提供误码校正，并且在存在数据破坏噪声的带宽或返回信道受限链路上进行可靠和有效的信息传输。 LDPC码还提供了在代码长度，线性处理复杂度和与代码长度相关联的并行性方面，指数速度接近信道容量的纠错性能。 它们还提供与二进制纠错码本身的解码复杂性相关的挑战，并且限制可实现的误码率的错误层。 提出了一种新的轻便半随机（RHS）解码算法，降低了高解码吞吐量应用的解码复杂度。 RHS算法使用基于随机解码算法的方法，但与LDPC解码器实现的传统方法有很大的不同。 RHS算法还导致称为重新编码的随机解码技术，其解决错误楼层限制。