公开(公告)号：US07560971B2

公开(公告)日：2009-07-14

申请号：US11956058

申请日：2007-12-13

Applicant: Walter W. Heikkila ,  Michael T. Johnson

Inventor： Walter W. Heikkila ,  Michael T. Johnson

IPC: H03L5/00

CPC classification number: H03K19/0013 ,  H03K19/00361 ,  H03K19/018521

Abstract: A level shift circuit for providing predictable outputs when VDDH is powering up and minimizing DC current when VDDL is powering up. The level shift circuit may have a control circuit that includes a first inverter with an input coupled to VDDL, one or more diodes coupled between the first inverter and its powering voltage supply, a second inverter coupled to an output of the first inverter (optionally coupled to its voltage supply via one or more diodes), a third inverter coupled to an output of the second control inverter, an NMOS transistor coupled to an output of the third inverter that forces the output of the level shift circuit to the ground voltage when enabled, and a PMOS transistor coupled to an output of the third inverter that disconnects a portion of the level shift circuit, and thus the output of the level shift circuit, from VDDH when disabled.

Abstract translation: 一个电平移位电路，用于在VDDH上电时提供可预测的输出，并在VDDL上电时最小化直流电流。 电平移位电路可以具有控制电路，其包括具有耦合到VDDL的输入的第一反相器，耦合在第一反相器和其供电电压源之间的一个或多个二极管，耦合到第一反相器的输出的第二反相器（可选地耦合 耦合到第二控制反相器的输出端的第三反相器，耦合到第三反相器的输出的NMOS晶体管，其在使能时迫使电平移位电路的输出为接地电压 以及耦合到第三反相器的输出的PMOS晶体管，其在禁用时断开电平移位电路的一部分，并且因此电平移位电路的输出从VDDH断开。

公开(公告)号：US20090153218A1

公开(公告)日：2009-06-18

申请号：US11956058

申请日：2007-12-13

Applicant: Walter W. Heikkila ,  Michael T. Johnson

Inventor： Walter W. Heikkila ,  Michael T. Johnson

IPC: H03L5/00

CPC classification number: H03K19/0013 ,  H03K19/00361 ,  H03K19/018521

Abstract: A level shift circuit for providing predictable outputs when VDDH is powering up and minimizing DC current when VDDL is powering up. The level shift circuit may have a control circuit that includes a first inverter with an input coupled to VDDL, one or more diodes coupled between the first inverter and its powering voltage supply, a second inverter coupled to an output of the first inverter (optionally coupled to its voltage supply via one or more diodes), a third inverter coupled to an output of the second control inverter, an NMOS transistor coupled to an output of the third inverter that forces the output of the level shift circuit to the ground voltage when enabled, and a PMOS transistor coupled to an output of the third inverter that disconnects a portion of the level shift circuit, and thus the output of the level shift circuit, from VDDH when disabled.

Abstract translation: 一个电平移位电路，用于在VDDH上电时提供可预测的输出，并在VDDL上电时最小化直流电流。 电平移位电路可以具有控制电路，其包括具有耦合到VDDL的输入的第一反相器，耦合在第一反相器和其供电电压源之间的一个或多个二极管，耦合到第一反相器的输出的第二反相器（可选地耦合 耦合到第二控制反相器的输出端的第三反相器，耦合到第三反相器的输出的NMOS晶体管，其在使能时迫使电平移位电路的输出为接地电压 以及耦合到第三反相器的输出的PMOS晶体管，其在禁用时断开电平移位电路的一部分，并且因此电平移位电路的输出从VDDH断开。

公开(公告)号：US07700409B2

公开(公告)日：2010-04-20

申请号：US11753669

申请日：2007-05-25

Applicant: Ronald J. Jensen ,  Walter W. Heikkila

Inventor： Ronald J. Jensen ,  Walter W. Heikkila

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/00014

Abstract: A design for stacking integrated circuits is described. Some integrated circuits have multiple signal pads that are common between a top integrated circuit and a bottom integrated circuit in an integrated circuit pair. These common pads are placed symmetrically on the integrated circuit. Unique signal pads are provided independently to each integrated circuit in a stack. An optional array of solder bumps placed over a central area of the integrated circuit may be used, which provides for heat transfer through the stack. When stacking multiple pairs of integrated circuits, the top integrated circuit in the integrated circuit stack pair serves as a spacer between the first and second pair of integrated circuits.

Abstract translation: 描述了堆叠集成电路的设计。 一些集成电路具有在集成电路对中的顶部集成电路和底部集成电路之间共同的多个信号焊盘。 这些公共焊盘对称放置在集成电路上。 单独的信号焊盘独立地提供给堆叠中的每个集成电路。 可以使用放置在集成电路的中心区域上的可选择的焊料凸块阵列，其提供通过堆叠的热传递。 当堆叠多对集成电路时，集成电路堆叠对中的顶部集成电路用作第一和第二对集成电路之间的间隔物。

公开(公告)号：US4141081A

公开(公告)日：1979-02-20

申请号：US866690

申请日：1978-01-03

Applicant: Merton A. Horne ,  Walter W. Heikkila

Inventor： Merton A. Horne ,  Walter W. Heikkila

IPC: G11C14/00 ,  G11C15/04 ,  G11C11/40

CPC classification number: G11C15/046

Abstract: A sense amplifier/latch circuit for a Metal Nitride Oxide (MNOS) Block Orgaized Random Access Memory (BORAM) with analog memory retention interrogation capabilities. The sense amplifier/latch circuit includes the associative memory transistors as an integral part of the latch as well as circuitry for increasing the switching speed of the sense latch in response to the differing conductances of the memory transistors when a row address voltage is applied to their gates.

Abstract translation: 用于具有模拟存储器保持询问能力的金属氮化物（MNOS）块组合随机存取存储器（BORAM）的读出放大器/锁存电路。 读出放大器/锁存电路包括作为锁存器的组成部分的关联存储器晶体管以及当行地址电压被施加到存储器晶体管时响应于存储器晶体管的不同电导而增大读出锁存器的开关速度的电路 大门

公开(公告)号：US08963590B2

公开(公告)日：2015-02-24

申请号：US12424446

申请日：2009-04-15

Applicant: Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

Inventor： Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

IPC: H03L7/00 ,  H03K3/02 ,  H03K17/04 ,  H03K17/22

CPC classification number: H03K17/223

Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal and its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage that offsets parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. A high resistance direct path to ground on an output node of the power-on reset circuit prevents residual charge from causing an undesired misfire.

Abstract translation: 提出了一种用于初始化电路的系统。 该系统采用具有阈值电压和可编程开关电路的上电复位电路。 上电复位电路具有用于检测参考电压的检测器电路和用于产生反映参考电压的输出电压的单侧锁存器。 检测器电路具有阈值，之后单侧锁存器被激活。 可编程开关电路接收上电复位电路的输出电压，并根据内部保险丝的状态产生使能信号及其补码。 上电复位电路的开关点提供输出电压的快速增加，以抵消可编程开关电路中的寄生漏电流，这可能导致不正确的使能信号输出。 在电源复位电路的输出节点上的高电阻直接接地路径可防止剩余电荷引起不期望的失火。

公开(公告)号：US20080309384A1

公开(公告)日：2008-12-18

申请号：US11762317

申请日：2007-06-13

Applicant: Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

Inventor： Joe G. Guimont ,  David K. Nelson ,  Walter W. Heikkila ,  Anuj Kohli

IPC: H03L7/00

CPC classification number: H03K17/223 ,  G06F1/24

Abstract: A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal arid its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage, offsetting parasitic leakage current in the programmable switch circuit that can result in improper enable signal output.

Abstract translation: 提出了一种用于初始化电路的系统。 该系统采用具有阈值电压和可编程开关电路的上电复位电路。 上电复位电路具有用于检测参考电压的检测器电路和用于产生反映参考电压的输出电压的单侧锁存器。 检测器电路具有阈值，之后单侧锁存器被激活。 可编程开关电路接收上电复位电路的输出电压，并根据内部保险丝的状态产生使能信号和补码。 上电复位电路的开关点提供输出电压的快速增加，抵消可编程开关电路中的寄生漏电流，从而导致不正确的使能信号输出。