知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.018 seconds)

    FANOUT WIRING STRUCTURE AND LIQUID CRYSTAL DISPLAY (LCD) PANEL USING THE SAME
    4.
    发明申请
    FANOUT WIRING STRUCTURE AND LIQUID CRYSTAL DISPLAY (LCD) PANEL USING THE SAME 审中-公开

    公开(公告)号：US20170235199A1

    公开(公告)日：2017-08-17

    申请号：US14907393

    申请日：2016-01-06

    Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

    Inventor： Cong WANG ,  Peng DU

    IPC: G02F1/1362 ,  G02F1/133 ,  G02F1/1345 ,  H01L27/12

    CPC classification number: G02F1/136286 ,  G02F1/13306 ,  G02F1/1345 ,  H01L27/124

    Abstract: A fanout wiring structure and LCD panel using the same are described. The fanout wiring structure comprises a substrate; a first wire region comprising first conductive wires with a first electric resistivity wherein each first conductive wire comprises a first end point and a second end point, and the first end point is electrically connected to the signal transmission interface; and a second wire region comprising second conductive wires with second electric resistivity wherein each second conductive wire comprises third end point and fourth end point, and the fourth end point is electrically connected to the signal receiving interface; wherein the second end point is electrically and correspondingly connected to the third end point, and each first conductive wire and each second conductive wire form either a collinear structure or a parallel connection structure to construct the fanout wiring structure for equalizing a resistance of each fanout wiring structure.

    SCANNING DRIVING CIRCUITS AND THE LIQUID CRYSTAL DEVICES WITH THE SAME
    6.
    发明申请
    SCANNING DRIVING CIRCUITS AND THE LIQUID CRYSTAL DEVICES WITH THE SAME 有权

    公开(公告)号：US20170169782A1

    公开(公告)日：2017-06-15

    申请号：US14888698

    申请日：2015-09-30

    Applicant: Shezhen China Star Optoelectronics Technology Co., Ltd. ,  Wuhan China Star Optoelectronics Technology Co., Ltd.

    Inventor： Cong WANG ,  Peng DU

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G02F1/13 ,  G09G2300/0809 ,  G09G2310/0243 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08

    Abstract: Provided are a scanning driving circuit and a liquid crystal display device. The scanning driving circuit comprises multiple cascaded scanning driving units (1). Each scanning driving unit (1) comprises an input module (100) for outputting a low-level signal and a plurality of driving circuits (200). Each driving circuit (200) corresponding drives one scanning line. Each driving circuit (200) comprises: a control module (210), for outputting a control signal according to the received low-level signal; an output module (220), and a pull-down module (230), for being connected or cut off according to the received control signal; scanning lines (G(N−1), G(N), G(N+1)), for outputting a high-level or low-level scanning driving signal to pixel units. When the output module (220) is cut off, the pull-down module (230) is connected, and the scanning lines (G(N−1), G(N), G(N+1)) output the low-level scan driving signals to the pixel units; and when the output module (220) is connected, the pull-down module (230) is cut off, and the scanning lines (G(N−1), G(N), G (N+1)) output high-level scanning driving signals to the pixel units. Accordingly, a circuit of the liquid crystal display device is simplified, and the space is saved, thereby facilitating the narrow-frame design of the liquid crystal display device.

    LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME
    8.
    发明申请
    LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME 审中-公开

    公开(公告)号：US20180130832A1

    公开(公告)日：2018-05-10

    申请号：US15863993

    申请日：2018-01-08

    Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. ,  Wuhan China Star Optoelectronics Technology Co., Ltd.

    Inventor： Cong WANG ,  Peng DU

    IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

    Abstract: An LTPS array substrate includes: a substrate on which a gate is disposed. An insulating layer and a polycrystalline silicon layer are disposed in sequence on the substrate and the gate. The insulating layer has an upper surface that is a plane. A source and a drain are disposed on the polycrystalline silicon layer and a pixel electrode is disposed on the insulating layer and a part of the drain. A plain passivation layer is disposed on the source and drain and includes a contact via formed therein at a location outside the polycrystalline silicon layer to expose a surface of one of the gate, the source, and the drain. A transparent electrode layer is disposed on the plain passivation layer to be electrically connected to the surface of the one of the gate, the source, and the drain that is exposed through the contact via.

Patent Agency Ranking