LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME

    公开(公告)号:US20180130832A1

    公开(公告)日:2018-05-10

    申请号:US15863993

    申请日:2018-01-08

    Inventor: Cong WANG Peng DU

    Abstract: An LTPS array substrate includes: a substrate on which a gate is disposed. An insulating layer and a polycrystalline silicon layer are disposed in sequence on the substrate and the gate. The insulating layer has an upper surface that is a plane. A source and a drain are disposed on the polycrystalline silicon layer and a pixel electrode is disposed on the insulating layer and a part of the drain. A plain passivation layer is disposed on the source and drain and includes a contact via formed therein at a location outside the polycrystalline silicon layer to expose a surface of one of the gate, the source, and the drain. A transparent electrode layer is disposed on the plain passivation layer to be electrically connected to the surface of the one of the gate, the source, and the drain that is exposed through the contact via.

    LIQUID CRYSTAL DISPLAY DEVICE AND ARRAY SUBSTRATE OF THE SAME
    3.
    发明申请
    LIQUID CRYSTAL DISPLAY DEVICE AND ARRAY SUBSTRATE OF THE SAME 有权
    液晶显示装置及其阵列基板

    公开(公告)号:US20170017125A1

    公开(公告)日:2017-01-19

    申请号:US14765834

    申请日:2015-07-17

    Inventor: Cong WANG

    Abstract: The present invention provides a liquid crystal display device and an array substrate of the same. The multiple pixel electrodes located at a same column allow lights having a same color to pass through. Each data line passes around at least one column of the multiple pixel electrodes row by row, and when each data line passes around two adjacent rows of the multiple pixel electrodes, opening directions are opposite. Pixel electrodes located at odd rows are connected with a same data line, pixel electrodes located at even rows are connected with a same data line, and pixel electrodes located at odd rows and even rows are respectively connected with different data lines. The present invention can reduce a bias generated at an edge of the color resist in order to improve a light leakage phenomenon when displaying.

    Abstract translation: 本发明提供一种液晶显示装置及其阵列基板。 位于同一列的多个像素电极允许具有相同颜色的光通过。 每个数据线逐行通过多个像素电极的至少一列,并且当每个数据线通过多个像素电极的两个相邻行时,打开方向相反。 位于奇数行的像素电极与相同的数据线连接,位于偶数行的像素电极与相同的数据线连接,位于奇数行和偶数行的像素电极分别与不同的数据线连接。 本发明可以减少在彩色抗蚀剂边缘产生的偏压,以便在显示时改善漏光现象。

    DISPLAY PANELS AND THE ARRAY SUBSTRATES THEREOF

    公开(公告)号:US20180231847A1

    公开(公告)日:2018-08-16

    申请号:US15513286

    申请日:2017-02-22

    Abstract: The present disclosure relates to a display panel and an array substrate including a plurality of pixel cells including colorful sub-pixels and one white sub-pixel. Each of the sub-pixels includes at least one sub-pixel electrode and at least one sub-pixel transistor corresponding to each of the sub-pixel electrode. The sub-pixel transistors are configured within the white sub-pixel to enhance an aperture rate of the colorful sub-pixels. As the sub-pixel transistors are configured within the same white sub-pixel, the brightness of the white sub-pixel may be decreased. At the same time, the aperture rate of the colorful sub-pixels may be greatly enhanced so as to enhance the performance of colorful images.

    FANOUT WIRING STRUCTURE AND LIQUID CRYSTAL DISPLAY (LCD) PANEL USING THE SAME

    公开(公告)号:US20170235199A1

    公开(公告)日:2017-08-17

    申请号:US14907393

    申请日:2016-01-06

    Inventor: Cong WANG Peng DU

    CPC classification number: G02F1/136286 G02F1/13306 G02F1/1345 H01L27/124

    Abstract: A fanout wiring structure and LCD panel using the same are described. The fanout wiring structure comprises a substrate; a first wire region comprising first conductive wires with a first electric resistivity wherein each first conductive wire comprises a first end point and a second end point, and the first end point is electrically connected to the signal transmission interface; and a second wire region comprising second conductive wires with second electric resistivity wherein each second conductive wire comprises third end point and fourth end point, and the fourth end point is electrically connected to the signal receiving interface; wherein the second end point is electrically and correspondingly connected to the third end point, and each first conductive wire and each second conductive wire form either a collinear structure or a parallel connection structure to construct the fanout wiring structure for equalizing a resistance of each fanout wiring structure.

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