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26 条记录 (耗时 0.022 秒)

    Method for configuring a finite impulse response filter in a programmable logic device
    1.
    发明授权
    Method for configuring a finite impulse response filter in a programmable logic device 有权
    用于在可编程逻辑器件中配置有限脉冲响应滤波器的方法

    公开(公告)号：US08386550B1

    公开(公告)日：2013-02-26

    申请号：US11533482

    申请日：2006-09-20

    申请人： Volker Mauer ,  Suleyman Sirri Demirsoy

    发明人： Volker Mauer ,  Suleyman Sirri Demirsoy

    IPC分类号： G06F17/10

    CPC分类号： H03H17/06

    摘要： A hybrid FIR filter includes a plurality of FIR filter units arranged as Direct Form FIR filters, connected together in an arrangement similar to a Transpose Form FIR filter. The hybrid filter arrangement may be used to configure a larger FIR filter in a programmable logic device having one or more specialized functional blocks, incorporating multipliers and adders, that are particularly well-suited for configuration as small Direct Form FIR filters.

    摘要翻译： 混合FIR滤波器包括布置成直接形式FIR滤波器的多个FIR滤波器单元，其以类似于转置形式FIR滤波器的布置连接在一起。 混合滤波器布置可以用于在具有一个或多个专用功能块（包括乘法器和加法器）的可编程逻辑器件中配置更大的FIR滤波器，其特别适合于作为小直接形式FIR滤波器的配置。

    QR decomposition in an integrated circuit device
    5.
    发明授权
    QR decomposition in an integrated circuit device 有权
    集成电路设备中的QR分解

    公开(公告)号：US08812576B1

    公开(公告)日：2014-08-19

    申请号：US13229820

    申请日：2011-09-12

    申请人： Volker Mauer

    发明人： Volker Mauer

    IPC分类号： G06F7/38

    CPC分类号： G06F17/16

    摘要： Circuitry for performing QR decomposition of an input matrix includes multiplication/addition circuitry for performing multiplication and addition/subtraction operations on a plurality of inputs, division/square-root circuitry for performing division and square-root operations on an output of the multiplication/addition circuitry, a first memory for storing the input matrix, a second memory for storing a selected vector of the input matrix, and a selector for inputting to the multiplication/addition circuitry any one or more of a vector of the input matrix, the selected vector, and an output of the division/square-root circuitry. On respective successive passes, a respective vector of the input matrix is read from a first memory into a second memory, and elements of a respective vector of an R matrix of the QR decomposition are computed and the respective vector of the input matrix in the first memory is replaced with the respective vector of the R matrix.

    摘要翻译： 用于执行输入矩阵的QR分解的电路包括用于对多个输入执行乘法和加法/减法运算的乘法/加法电路，用于对乘法/加法的输出执行除法和平方根运算的除法/平方根电路 电路，用于存储输入矩阵的第一存储器，用于存储输入矩阵的选定向量的第二存储器，以及用于向乘法/加法电路输入输入矩阵的向量中的一个或多个的选择器，所选择的向量 ，以及除法/平方根电路的输出。 在相应的连续遍中，将输入矩阵的相应向量从第一存储器读取到第二存储器中，并且计算QR分解的R矩阵的相应向量的元素，并且输入矩阵的相应向量在第一存储器 存储器被R矩阵的相应矢量代替。

    Adaptive sampling rate converter
    6.
    发明授权
    Adaptive sampling rate converter 失效
    自适应采样率转换器

    公开(公告)号：US07680233B1

    公开(公告)日：2010-03-16

    申请号：US12061586

    申请日：2008-04-02

    申请人： Volker Mauer

    发明人： Volker Mauer

    IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

    CPC分类号： H03H17/0628 ,  H03H17/028 ,  H04L7/0029 ,  Y10S370/914

    摘要： Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as “clock jitter” and/or “clock drift” effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment value Δμ based on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offset μ as necessary. Such systems are useful in software defined radio and the like and may be implemented on a variety of devices, including PLDs.

    摘要翻译： 用于调整采样率转换中使用的相位偏移的装置，方法和技术使用Farrow结构等来补偿时钟问题，例如“时钟抖动”和/或“时钟漂移”效应，这通常在一个时钟是真实的 独立于其他。 基于跨过渡接口和/或通过缓冲器的时钟域之间的测量数据流，计算相位偏移调整值＆Dgr;μ。 在使用输出FIFO缓冲器的情况下，测量的数据流量值表示写入FIFO缓冲器和从FIFO缓冲器读取的数据字的数量，例如存储在FIFO缓冲器中的当前数据字的数量或表示 数据字写入FIFO缓冲区。 将测量的数据流值与目标数据流值进行比较，其可以是值的范围。 相位偏移调整值可以根据需要连续地和/或周期性地更新和/或重新计算并被添加到或从相位偏移μ中减去。 这样的系统在软件定义的无线电等中是有用的，并且可以在包括PLD的各种设备上实现。

    Method and apparatus for implementing a multi-step pseudo random sequence generator
    8.
    发明授权
    Method and apparatus for implementing a multi-step pseudo random sequence generator 有权
    用于实现多步伪随机序列发生器的方法和装置

    公开(公告)号：US06910056B1

    公开(公告)日：2005-06-21

    申请号：US09924675

    申请日：2001-08-08

    申请人： Volker Mauer

    发明人： Volker Mauer

    IPC分类号： G06F1/02 ,  G06F7/58

    CPC分类号： G06F7/584 ,  G06F2207/583

    摘要： A method for implementing a pseudo random sequence (PRS) generator is disclosed. Relationships between outputs of flip-flops of an initial model PRS generator at a current time step t with the outputs of the flip-flops at a time step t-n is determined, where n is a number of coefficients to be generated per time step. Flip-flops in the multi-step PRS generator are coupled in response to the relationships between the outputs of the flip-flops at the current time step t with the output of the flip-flops at the time step t-n.

    摘要翻译： 公开了一种用于实现伪随机序列（PRS）生成器的方法。 确定在当前时间步长t的初始模型PRS发生器的触发器的输出与时间步长t-n处触发器的输出之间的关系，其中n是每个时间步长将要产生的系数的数量。 多级PRS发生器中的触发器响应于在当前时间步长t的触发器的输出与时间步长t-n的触发器的输出之间的关系而耦合。

    Peak windowing for crest factor reduction
    9.
    发明授权
    Peak windowing for crest factor reduction 有权
    峰值窗口降低波峰因数

    公开(公告)号：US07586995B1

    公开(公告)日：2009-09-08

    申请号：US11109536

    申请日：2005-04-18

    申请人： Volker Mauer ,  Kulwinder Dhanoa ,  Paul Metzgen

    发明人： Volker Mauer ,  Kulwinder Dhanoa ,  Paul Metzgen

    IPC分类号： H04L25/49

    CPC分类号： H04L27/3411

    摘要： In order to reduce the crest factor of a signal for power amplification, a windowing function is applied. The windowing function that is applied is a triangular windowing function. The use of this function produces good results when those results are measured in terms of their effect on a transmitted signal in a WCDMA communications system. The filter for performing the triangular windowing function receives the signal, and applies it to a first delay element. The output from the first delay element is applied to a second delay element. An adder forms a weighted sum of the received signal and the signals at the outputs of the first delay element and the second delay element. A first accumulator is connected to receive an input from the adder and provides a first accumulator output, while a second accumulator is connected to receive an input from the first accumulator output and provides a second accumulator output.

    摘要翻译： 为了降低用于功率放大的信号的波峰因数，应用窗口功能。 应用的窗口功能是三角窗口功能。 当这些结果在其对WCDMA通信系统中的发射信号的影响方面测量时，使用该功能产生良好的结果。 用于执行三角窗函数的滤波器接收信号，并将其施加到第一延迟元件。 来自第一延迟元件的输出被施加到第二延迟元件。 加法器形成接收信号和第一延迟元件和第二延迟元件的输出处的信号的加权和。 连接第一累加器以从加法器接收输入并提供第一累加器输出，而第二累加器被连接以接收来自第一累加器输出的输入并提供第二累加器输出。

    Method and apparatus for extracting data from an oversampled bit stream
    10.
    发明授权
    Method and apparatus for extracting data from an oversampled bit stream 失效
    用于从过采样比特流中提取数据的方法和装置

    公开(公告)号：US06944577B1

    公开(公告)日：2005-09-13

    申请号：US10728228

    申请日：2003-12-03

    申请人： Volker Mauer ,  James Tyson

    发明人： Volker Mauer ,  James Tyson

    IPC分类号： G06F15/00

    CPC分类号： H04L7/0338 ,  H04L7/007

    摘要： Apparatus and method extract data from a data stream. The method includes oversampling the data stream, performing first processing on adjacent bits of the oversampled data stream, performing second processing the results of the first processing, comparing the results of the second processing, and selecting an alignment of data based on the comparison. The method can be efficiently implemented using accumulators, delay elements, and XOR elements. In this manner, data may be extracted from the data stream despite a varying or unknown phase or duty cycle, or in the presence of jitter.

    摘要翻译： 设备和方法从数据流中提取数据。 该方法包括对数据流进行过采样，对过采样数据流的相邻位执行第一处理，对第一处理的结果进行第二处理，比较第二处理的结果，以及基于比较选择数据的对齐。 可以使用累加器，延迟元件和XOR元件来有效地实现该方法。 以这种方式，尽管变化或未知的相位或占空比，或者在存在抖动的情况下，也可以从数据流中提取数据。