公开(公告)号：US06944577B1

公开(公告)日：2005-09-13

申请号：US10728228

申请日：2003-12-03

申请人： Volker Mauer ,  James Tyson

发明人： Volker Mauer ,  James Tyson

IPC分类号： G06F15/00

CPC分类号： H04L7/0338 ,  H04L7/007

摘要： Apparatus and method extract data from a data stream. The method includes oversampling the data stream, performing first processing on adjacent bits of the oversampled data stream, performing second processing the results of the first processing, comparing the results of the second processing, and selecting an alignment of data based on the comparison. The method can be efficiently implemented using accumulators, delay elements, and XOR elements. In this manner, data may be extracted from the data stream despite a varying or unknown phase or duty cycle, or in the presence of jitter.

摘要翻译： 设备和方法从数据流中提取数据。 该方法包括对数据流进行过采样，对过采样数据流的相邻位执行第一处理，对第一处理的结果进行第二处理，比较第二处理的结果，以及基于比较选择数据的对齐。 可以使用累加器，延迟元件和XOR元件来有效地实现该方法。 以这种方式，尽管变化或未知的相位或占空比，或者在存在抖动的情况下，也可以从数据流中提取数据。

公开(公告)号：US07263623B1

公开(公告)日：2007-08-28

申请号：US10814949

申请日：2004-03-30

申请人： Andrew Crosland ,  James Tyson ,  Fabio Petrassem de Sousa ,  Andrew Draper

发明人： Andrew Crosland ,  James Tyson ,  Fabio Petrassem de Sousa ,  Andrew Draper

IPC分类号： G06F1/00 ,  G06F13/12

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A microprocessor-based system includes multiple peripherals, which can be accessed by the microprocessor over a system bus, with the aid of address decoding logic. Depending on the required functionality of the system at any time, one or more of the peripherals can be disabled. When a peripheral device is disabled, the address decoding logic of the system is modified to ensure that no attempts are made to access that peripheral device.

摘要翻译： 基于微处理器的系统包括多个外设，借助于地址解码逻辑，微处理器可以通过系统总线访问。 随着系统所需功能的不同，一个或多个外设可以被禁用。 当外围设备被禁用时，系统的地址解码逻辑被修改以确保没有尝试访问该外围设备。

公开(公告)号：US09047329B1

公开(公告)日：2015-06-02

申请号：US13458943

申请日：2012-04-27

申请人： James Tyson

发明人： James Tyson

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F17/30 ,  G06F12/08

CPC分类号： G06F17/3033 ,  G06F12/0292 ,  G06F12/0864 ,  G06F17/30952

摘要： In one aspect, a device is configured to provide a lookup operation for looking up a data value stored in a result table. The device includes several data tables for storing keys, or compressed representations of keys, associated with data values stored in the result table. During an example lookup operation, storage locations included within the data tables are searched for a particular key, or compressed representations of the key. If the key is found, the storage location is used to identify a memory address associated with the result table. In some implementations, the data tables are accessed in parallel to provide a lookup operation having a fixed latency. Storage locations within the data tables also are arranged to reduce the amount of memory used to implement each data table. In some implementations, the data tables are configured to use no more than one result table access per lookup operation.

摘要翻译： 在一个方面，设备被配置为提供用于查找存储在结果表中的数据值的查找操作。 该设备包括用于存储与存储在结果表中的数据值相关联的密钥或密钥的压缩表示的几个数据表。 在示例查找操作期间，搜索包含在数据表内的存储位置用于特定密钥或密钥的压缩表示。 如果找到密钥，则存储位置用于标识与结果表相关联的存储器地址。 在一些实现中，并行访问数据表以提供具有固定等待时间的查找操作。 数据表中的存储位置也被设置为减少用于实现每个数据表的内存量。 在一些实现中，数据表被配置为使用每个查找操作不超过一个结果表访问。

公开(公告)号：US06745369B1

公开(公告)日：2004-06-01

申请号：US09668665

申请日：2000-09-22

申请人： Roger May ,  James Tyson ,  Edward Flaherty ,  Mark Dickinson

发明人： Roger May ,  James Tyson ,  Edward Flaherty ,  Mark Dickinson

IPC分类号： G06F1576

CPC分类号： G06F13/405

摘要： A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

摘要翻译： 一种用于芯片系统的多总线架构，包括用于将各个总线主机的时钟频率与其正在访问的外设进行去耦的桥。 每个桥接器连接到需要访问其接口的外设的系统中的所有总线主机。

公开(公告)号：US06625568B2

公开(公告)日：2003-09-23

申请号：US10039835

申请日：2001-10-23

申请人： James Tyson

发明人： James Tyson

IPC分类号： B22D1116

CPC分类号： A47L15/0049 ,  A47L15/22 ,  A47L15/46 ,  A47L2401/06 ,  A47L2401/24 ,  A47L2401/32 ,  A47L2501/26 ,  G01M99/005

摘要： Sound detection techniques and sound discrimination techniques are used to analyze the real time sounds generated during the operation of cleaning heads operating within a vessel to determine if the cleaning heads are operating properly. During a typical cleaning operation pressurized cleaning solution is dispensed through a rotating nozzle assembly inside the vessel. As the nozzles rotate the spray moves about the interior of the vessel creating a unique sound pattern. By placing one or more pickups on the exterior of the vessel the sound is captured and fed to an analyzing device for analysis. Key properties such as, but not limited to, sound pressure levels, amplitude variations, spectral content, and rotational information are extracted and analyzed against the reference parameters.

公开(公告)号：US6109391A

公开(公告)日：2000-08-29

申请号：US316966

申请日：1999-05-24

申请人： James Tyson

发明人： James Tyson

IPC分类号： E04G1/30 ,  E06C7/16

CPC分类号： E04G1/30 ,  E06C7/16

摘要： A ladder scaffold is suspended from rods inserted through the hollow rungs of a ladder. The ladder scaffold includes at least two ladders, at least two platform braces, and a platform. Each platform brace has three rods, two long members, and two short members. Two of the rods are inserted through the hollow rungs of a ladder. The long members are attached to the ends of one of the rods and extend downwards from the ladder. The short members are attached to the ends of the second rod. The short members extend horizontally from the ladder towards the surface against which the ladders are leaning. The third rod serves as a pivot point between the long members and the short members. The platform is supported by the short members and extends between the ladders. The long and short members can be attached to the rods at various points, so that the platform can be leveled. The ladder scaffold folds for easy transport. The ladder scaffold may or may not include a safety bar.

摘要翻译： 梯子脚架悬挂在穿过梯子的空心梯级的杆上。 梯子脚手架包括至少两个梯子，至少两个平台支架和平台。 每个平台支架有三个杆，两个长的成员和两个短的成员。 两根杆插入梯子的空心梯级。 长的构件附接到一个杆的端部并从梯子向下延伸。 短构件附接到第二杆的端部。 短的构件从梯子水平延伸到梯子倾斜的表面。 第三杆用作长构件和短构件之间的枢轴点。 该平台由短部件支撑，并在梯子之间延伸。 长和短构件可以在各个点附接到杆，使得平台可以平整。 梯子脚手架折叠，方便运输。 梯子脚手架可能包括或可能不包括安全栏。

公开(公告)号：US07298299B1

公开(公告)日：2007-11-20

申请号：US10970886

申请日：2004-10-21

申请人： Colman Cheung ,  Ray Schouten ,  Stephane Cauneau ,  James Tyson

发明人： Colman Cheung ,  Ray Schouten ,  Stephane Cauneau ,  James Tyson

IPC分类号： H03M9/00

CPC分类号： H04L7/0338

摘要： A receiving device oversamples incoming serial data using multiple phases of its system clock. The device detects an initial edge in the set of samples and selects a sample based on the location of the initial edge. A first bit is set to the value of the selected sample. A portion of the set of samples following the initial edge. If an edge is detected, then a sample is selected based upon the location of the detected edge and the next bit is set to the value of the selected sample. If an edge is not detected within this portion, then the position of the next edge is estimated. A sample is selected based upon the location of the estimated edge and the next bit is set to the value of the selected sample. The analysis is repeated for another portion of the set of samples following the newest edge.

摘要翻译： 接收设备使用其系统时钟的多个相位来超过输入的串行数据。 设备检测样本集中的初始边缘，并根据初始边缘的位置选择样本。 第一位设置为所选样本的值。 初始边缘之后的一组样本的一部分。 如果检测到边缘，则根据检测到的边缘的位置选择样本，并将下一个位设置为所选样本的值。 如果在该部分内没有检测到边缘，则估计下一个边缘的位置。 基于估计边缘的位置选择一个样本，并将下一个位设置为所选样本的值。 对最接近最新边的样本集的另一部分重复分析。

公开(公告)号：US07081773B1

公开(公告)日：2006-07-25

申请号：US10886914

申请日：2004-07-07

申请人： Roger May ,  James Tyson ,  Mark Dickinson

发明人： Roger May ,  James Tyson ,  Mark Dickinson

IPC分类号： H03K19/173

CPC分类号： H03K19/17776 ,  H03K19/17752 ,  H03K19/1776

摘要： A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from an external memory device, and a second store, in which a copy of the configuration data is maintained, with the functionality of the programmable logic device being determined by the copy of the configuration data, thereby allowing additional configuration data to be downloaded from the external memory device into the first store, while maintaining the functionality of the device. This allows the device to be used to provide two different functionalities, and to be switched between these two functionalities with minimal delay for reconfiguration of the device.

摘要翻译： 可编程逻辑器件可在两个功能之间进行重新配置，同时它正在使用中。 可编程逻辑器件具有可从外部存储器件下载配置数据的第一存储器和维持配置数据的副本的第二存储器，其中可编程逻辑器件的功能由 配置数据的副本，从而允许在维护设备的功能的同时将附加配置数据从外部存储设备下载到第一存储器中。 这允许该设备用于提供两种不同的功能，并且以最小的延迟在这两个功能之间切换以重新配置设备。

公开(公告)号：US07038488B1

公开(公告)日：2006-05-02

申请号：US10836965

申请日：2004-04-30

申请人： James Tyson

发明人： James Tyson

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/17744 ,  H03K19/17732

摘要： A programmable logic device (PLD) includes a transceiver, configurable phase-locked loop (PLL) circuits, and programmable logic circuits. The logic circuits and PLL circuits are programmed to enable the transceiver to flexibly respond to various types of input serial data signals, and to flexibly generate various types of output serial data signals, such as Serial Digital Interface (SDI) signals and High Definition SDI (HD-SDI) signals. This allows the PLD to be used in a wide variety of systems without requiring custom external components.

摘要翻译： 可编程逻辑器件（PLD）包括收发器，可配置锁相环（PLL）电路和可编程逻辑电路。 逻辑电路和PLL电路被编程为使得收发器能够灵活地响应各种类型的输入串行数据信号，并且灵活地生成各种类型的输出串行数据信号，例如串行数字接口（SDI）信号和高清SDI（ HD-SDI）信号。 这使得PLD可以在各种系统中使用，而不需要定制的外部组件。

公开(公告)号：US08874866B1

公开(公告)日：2014-10-28

申请号：US12693288

申请日：2010-01-25

申请人： James Tyson

发明人： James Tyson

IPC分类号： G06F12/00 ,  G06F17/30 ,  G06F12/14

CPC分类号： G06F12/1466 ,  G06F17/30946 ,  G06F17/30949

摘要： Embodiments of the present invention provide methods of reading data from and writing data to a memory, computer program products for performing such methods, and apparatus for reading data from and writing data to, a memory, which apparatus may be implemented, for example, as a Field Programmable Gate Array (FPGA). A key associated with data to be read from or written to the memory is converted into two separate values, which values are themselves converted into first and second index values, each having an associated signature value. The index values are used as indices to a signature table containing a signature value for each data entry stored in the memory from which data is to be read or to which data is to be written. In a read operation, a signature of the signature table which matches one of the signature values derived from the key is identified and a read address is calculated based on the index value associated with the matching signature value derived from the key. In a write operation, a signature value is written to the signature table at an address corresponding to one of the index values derived from the key, and a write address is calculated based on that index value.

摘要翻译： 本发明的实施例提供了从存储器读取数据和向存储器写入数据的方法，用于执行这些方法的计算机程序产品，以及用于从存储器读取数据并将数据写入存储器的装置，该装置可以被实现为例如 现场可编程门阵列（FPGA）。 与要从存储器读取或写入存储器的数据相关联的键被转换为两个单独的值，这些值本身被转换为第一和第二索引值，每个具有相关联的签名值。 索引值用作签名表的索引，该签名表包含存储在要从中读取数据的存储器中的每个数据条目的签名值或要写入哪个数据的签名表。 在读取操作中，识别与从密钥导出的签名值中的一个匹配的签名表的签名，并且基于与从密钥导出的匹配签名值相关联的索引值来计算读取地址。 在写入操作中，签名值以对应于从密钥导出的索引值之一的地址写入签名表，并且基于该索引值计算写入地址。