公开(公告)号：US20190378846A1

公开(公告)日：2019-12-12

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US10580780B2

公开(公告)日：2020-03-03

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L23/62 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/28

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US10008615B1

公开(公告)日：2018-06-26

申请号：US15437740

申请日：2017-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Sheng Feng ,  Chi-Cheng Huang ,  Ping-Chia Shih ,  Hung-Wei Lin ,  Yu-Chun Chen ,  Ling-Hsiu Chou ,  An-Hsiu Cheng

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.

公开(公告)号：US20160306912A1

公开(公告)日：2016-10-20

申请号：US14690481

申请日：2015-04-20

Applicant: United Microelectronics Corp.

Inventor： Yen-Hung Chen ,  Chin-Lung Lin ,  Kuan-Wen Fang ,  Po-Ching Su ,  Hung-Wei Lin ,  Sheng-Lung Teng ,  Lun-Wen Yeh

IPC: G06F17/50 ,  H01L21/768 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  H01L21/76807

Abstract: An optical proximity correction (OPC) process is provided. The method comprising receiving a first pattern corresponding to a first structure of a semiconductor structure, and a second pattern corresponding to a second structure of said semiconductor structure. Next, a first OPC process is performed for the first pattern to obtain a revised first pattern, wherein the revised first pattern has a first shift regarding to the first pattern. A second OPC process is performed for the second pattern to obtain a revised second pattern, wherein the second OPC process comprises moving the second pattern according to the first shift.

Abstract translation: 提供光学邻近校正（OPC）过程。 该方法包括接收对应于半导体结构的第一结构的第一图案，以及对应于所述半导体结构的第二结构的第二图案。 接下来，对第一图案执行第一OPC处理以获得修改的第一图案，其中修改的第一图案具有关于第一图案的第一移位。 对第二图案执行第二OPC处理以获得修订的第二图案，其中第二OPC处理包括根据第一移位移动第二图案。

公开(公告)号：US20180182900A1

公开(公告)日：2018-06-28

申请号：US15437740

申请日：2017-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Sheng Feng ,  Chi-Cheng Huang ,  Ping-Chia Shih ,  Hung-Wei Lin ,  Yu-Chun Chen ,  Ling-Hsiu Chou ,  An-Hsiu Cheng

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L21/823462 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/66833

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.

公开(公告)号：US20170200729A1

公开(公告)日：2017-07-13

申请号：US14993101

申请日：2016-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tseng-Fang Dai ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kun-I Chou ,  Hung-Wei Lin ,  Ching-Wen Yang

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/518 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/513 ,  H01L29/66545

Abstract: An integrated circuit process includes the following steps. A substrate including a flash cell area and a logic area is provided. A first sacrificial gate on the substrate of the flash cell area and a second sacrificial gate on the substrate of the logic area are formed, and a dielectric layer covers the substrate beside the first sacrificial gate and the second sacrificial gate. The first sacrificial gate is removed to forma first recess in the dielectric layer. An oxide/nitride/oxide layer is formed to conformally cover surfaces of the first recess. An integrated circuit formed by said integrated circuit process is also provided.

公开(公告)号：US09563738B2

公开(公告)日：2017-02-07

申请号：US14690481

申请日：2015-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hung Chen ,  Chin-Lung Lin ,  Kuan-Wen Fang ,  Po-Ching Su ,  Hung-Wei Lin ,  Sheng-Lung Teng ,  Lun-Wen Yeh

IPC: G06F17/50 ,  G03F1/36 ,  H01L21/768

CPC classification number: G06F17/5081 ,  G03F1/36 ,  H01L21/76807

Abstract: An optical proximity correction (OPC) process is provided. The method comprising receiving a first pattern corresponding to a first structure of a semiconductor structure, and a second pattern corresponding to a second structure of said semiconductor structure. Next, a first OPC process is performed for the first pattern to obtain a revised first pattern, wherein the revised first pattern has a first shift regarding to the first pattern. A second OPC process is performed for the second pattern to obtain a revised second pattern, wherein the second OPC process comprises moving the second pattern according to the first shift.

Abstract translation: 提供光学邻近校正（OPC）过程。 该方法包括接收对应于半导体结构的第一结构的第一图案，以及对应于所述半导体结构的第二结构的第二图案。 接下来，对第一图案执行第一OPC处理以获得修改的第一图案，其中修改的第一图案具有关于第一图案的第一移位。 对第二图案执行第二OPC处理以获得修订的第二图案，其中第二OPC处理包括根据第一移位移动第二图案。