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    LAYOUT OF INTEGRATED CIRCUIT
    1.
    发明申请
    LAYOUT OF INTEGRATED CIRCUIT 有权

    公开(公告)号：US20230096645A1

    公开(公告)日：2023-03-30

    申请号：US17715974

    申请日：2022-04-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

    IPC: H01L27/02

    Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

    INTEGRATED CIRCUIT LAYOUT
    3.
    发明申请
    INTEGRATED CIRCUIT LAYOUT 有权

    公开(公告)号：US20220344321A1

    公开(公告)日：2022-10-27

    申请号：US17348784

    申请日：2021-06-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Chien-Hung Chen ,  Chun-Hsien Lin

    IPC: H01L27/02

    Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

    Speed-up charge pump and phase-locked loop and method for operating the same
    5.
    发明授权
    Speed-up charge pump and phase-locked loop and method for operating the same 有权

    公开(公告)号：US11115033B1

    公开(公告)日：2021-09-07

    申请号：US17065414

    申请日：2020-10-07

    Applicant: United Microelectronics Corp.

    Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Yu-Lin Chen

    IPC: H03L7/089 ,  H03L7/099

    Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

    Integrated circuits with standard cell
    6.
    发明授权
    Integrated circuits with standard cell 有权

    公开(公告)号：US10090289B1

    公开(公告)日：2018-10-02

    申请号：US15813163

    申请日：2017-11-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

    IPC: H01L27/02 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528

    Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.

    Semiconductor layout structure and designing method thereof
    7.
    发明授权
    Semiconductor layout structure and designing method thereof 有权

    公开(公告)号：US09898569B2

    公开(公告)日：2018-02-20

    申请号：US14852635

    申请日：2015-09-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

    IPC: H01L21/70 ,  G06F17/50 ,  H01L27/02

    CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

    Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

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