公开(公告)号：US10003018B1

公开(公告)日：2018-06-19

申请号：US15589613

申请日：2017-05-08

Applicant: Tokyo Electron Limited

Inventor： Ian Colgan ,  Ioan Domsa ,  George Eyres ,  Saito Makoto ,  Noel O'Shaughnessy ,  Toru Ishii ,  David Hurley

IPC: H01L21/00 ,  H01L43/12 ,  H01L27/22 ,  C21D9/00 ,  H01L21/477 ,  C21D1/42 ,  C21D1/54 ,  G11C11/16

CPC classification number: H01L43/12 ,  C21D1/42 ,  C21D1/54 ,  C21D9/0018 ,  H01L27/222 ,  Y02P10/253

Abstract: Embodiments are described for annealing systems and related methods to process microelectronic workpieces using vertical multi-batch perpendicular magnetic annealing systems that allow for a side-by-side configuration of multiple annealing systems to satisfy reduced footprint requirements.

公开(公告)号：US12211907B2

公开(公告)日：2025-01-28

申请号：US17397159

申请日：2021-08-09

Applicant: Tokyo Electron Limited

Inventor： Dina H. Triyoso ,  Robert D. Clark ,  David Hurley ,  Ian Colgan

IPC: H01L21/28

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US11837652B2

公开(公告)日：2023-12-05

申请号：US17662579

申请日：2022-05-09

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L29/6684 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/02667 ,  H01L21/67098

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US12235045B2

公开(公告)日：2025-02-25

申请号：US17656588

申请日：2022-03-25

Applicant: Tokyo Electron Limited

Inventor： Ian Colgan ,  Ioan Domsa ,  George Eyres ,  Bartlomiej Burkowicz ,  Barry Clarke ,  David Hurley ,  Einstein Noel Abarra

IPC: H01L21/00 ,  F27B17/00 ,  F27D3/00 ,  H01L21/324 ,  F27D7/06

Abstract: The disclosure describes equipment for magnetic annealing of a substrate, the equipment including: an anneal chamber configured to heat and cool a substrate held at a soak location along a first direction in the anneal chamber, the anneal chamber including: a heater, a cooler, and a substrate lifter including a substrate holder, where the substrate holder is configured to support a substrate oriented such that the first direction is perpendicular to a major surface of the substrate; and a magnet assembly configured to establish a homogeneous zone in the anneal chamber, the soak location being within the homogeneous zone, the homogeneous zone including a region of magnetic field.

公开(公告)号：US11335792B2

公开(公告)日：2022-05-17

申请号：US16841342

申请日：2020-04-06

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US11894240B2

公开(公告)日：2024-02-06

申请号：US17185231

申请日：2021-02-25

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  Ian Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson ,  Gerrit J. Leusink ,  Robert Clark ,  Dina Triyoso

IPC: H01L21/326 ,  H01L21/04 ,  H01L21/42 ,  H01L21/02

CPC classification number: H01L21/326 ,  H01L21/02107 ,  H01L21/0425 ,  H01L21/42

Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

公开(公告)号：US20230304741A1

公开(公告)日：2023-09-28

申请号：US17656588

申请日：2022-03-25

Applicant: Tokyo Electron Limited

Inventor： Ian Colgan ,  Ioan Domsa ,  George Eyres ,  Bartlomiej Burkowicz ,  Barry Clarke ,  David Hurley ,  Einstein Noel Abarra

IPC: F27B17/00 ,  H01L21/324 ,  F27D3/00

CPC classification number: F27B17/0025 ,  H01L21/324 ,  F27D3/0084 ,  F27D2007/066

Abstract: The disclosure describes equipment for magnetic annealing of a substrate, the equipment including: an anneal chamber configured to heat and cool a substrate held at a soak location along a first direction in the anneal chamber, the anneal chamber including: a heater, a cooler, and a substrate lifter including a substrate holder, where the substrate holder is configured to support a substrate oriented such that the first direction is perpendicular to a major surface of the substrate; and a magnet assembly configured to establish a homogeneous zone in the anneal chamber, the soak location being within the homogeneous zone, the homogeneous zone including a region of magnetic field.

公开(公告)号：US11527345B2

公开(公告)日：2022-12-13

申请号：US16466824

申请日：2018-01-03

Applicant: TOKYO ELECTRON LIMITED

Inventor： Ian Colgan ,  Ioan Domsa ,  George Eyres ,  Toru Ishii ,  Makoto Saito ,  David Hurley ,  Noel O'Shaughnessy ,  Barry Clarke ,  Gerhardus Van Der Linde ,  Pat Hughes

IPC: H01F13/00 ,  C21D1/26 ,  G01R33/02 ,  G01R33/12

Abstract: An apparatus for magnetic annealing one or more workpieces, and a method of operating the apparatus, are described. The apparatus includes: a workpiece holder configured to support one or more workpieces, wherein the one or more workpieces having at least one substantially planar surface; an optional workpiece heating system configured to elevate the one or more workpieces to an anneal temperature; and a magnet assembly having a first magnet and a second magnet, the first and second magnets defining a gap between opposing poles of each magnet, wherein the magnet assembly is arranged to generate a magnetic field substantially perpendicular to the planar surface of the one or more workpieces.

公开(公告)号：US20220262921A1

公开(公告)日：2022-08-18

申请号：US17662579

申请日：2022-05-09

Applicant: Tokyo Electron Limited

Inventor： David Hurley ,  Ioan Domsa ,  lan Colgan ,  Gerhardus Van Der Linde ,  Patrick Hughes ,  Maciej Burel ,  Barry Clarke ,  Mihaela Ioana Popovici ,  Lars-Ake Ragnarsson

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/67

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.

公开(公告)号：US20210367046A1

公开(公告)日：2021-11-25

申请号：US17397159

申请日：2021-08-09

Applicant: Tokyo Electron Limited

Inventor： Dina H. Triyoso ,  Robert D. Clark ,  David Hurley ,  Ian Colgan

IPC: H01L21/28

Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.