公开(公告)号：US20060047775A1

公开(公告)日：2006-03-02

申请号：US10928451

申请日：2004-08-27

申请人： Timo Bruck ,  Victor Wong ,  Thomas Hammer

发明人： Timo Bruck ,  Victor Wong ,  Thomas Hammer

IPC分类号： G06F15/16

CPC分类号： H04N7/17318 ,  H04L67/32 ,  H04N21/4334 ,  H04N21/44218 ,  H04N21/44227 ,  H04N21/458 ,  H04N21/4622 ,  H04N21/472

摘要： Methods and apparatus for managing download of content to a client device are disclosed. In one aspect, the download process is optimized for bandwidth usage by using criteria such as time of day, level of network activity and priority of download. In another aspect, download of content is prioritized based on certain rules, user inputs and pre-emptive events on the client device. A computer program embodying these methods and a multimedia client device adapted to run this program are also disclosed.

摘要翻译： 公开了一种用于管理向客户端设备下载内容的方法和装置。 在一个方面，通过使用诸如时间，网络活动级别和下载优先级之类的标准来优化用于带宽使用的下载过程。 在另一方面，基于客户端设备上的某些规则，用户输入和优先事件来优先确定内容的下载。 还公开了体现这些方法的计算机程序和适于运行该程序的多媒体客户端设备。

公开(公告)号：US08687459B2

公开(公告)日：2014-04-01

申请号：US13108854

申请日：2011-05-16

申请人： Victor Wong ,  Alan Wilson ,  Christopher K. Morzano

发明人： Victor Wong ,  Alan Wilson ,  Christopher K. Morzano

IPC分类号： G11C8/18

CPC分类号： G11C7/20 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4094

摘要： Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.

摘要翻译： 提供了操作存储器件和存储器件的方法。 例如，提供了一种操作存储器阵列的方法，其包括同步路径和异步路径。 向同步路径提供写入自动去电信号，并且向异步路径提供各种存储体地址信号。 在另一个实施例中，存储体地址信号的启动可以与写入自动补偿信号的断言异步地提供。

公开(公告)号：US20110216621A1

公开(公告)日：2011-09-08

申请号：US13108854

申请日：2011-05-16

申请人： Victor Wong ,  Alan Wilson ,  Christopher K. Morzano

发明人： Victor Wong ,  Alan Wilson ,  Christopher K. Morzano

IPC分类号： G11C8/18

CPC分类号： G11C7/20 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/4094

摘要： Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.

摘要翻译： 提供了操作存储器件和存储器件的方法。 例如，提供了一种操作存储器阵列的方法，其包括同步路径和异步路径。 向同步路径提供写入自动去电信号，并且向异步路径提供各种存储体地址信号。 在另一个实施例中，存储体地址信号的启动可以与写入自动补偿信号的断言异步地提供。

公开(公告)号：US20110194367A1

公开(公告)日：2011-08-11

申请号：US12702037

申请日：2010-02-08

申请人： Victor Wong ,  William F. Jones ,  Seth A. Eichmeyer

发明人： Victor Wong ,  William F. Jones ,  Seth A. Eichmeyer

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/02 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/783

摘要： Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to the digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.

摘要翻译： 提供了用于刷新的存储器，系统和方法，例如具有划分为部分的存储器单元阵列的存储器。 存储器包括具有数字线的替换元件，以及耦合到存储单元阵列的至少一个部分的数字线的耦合到替换元件的数字线的检测电路。 存储器包括控制逻辑，其被配置为当相对于替换元件的存储器单元阵列的非相邻部分被刷新时，在出现时有选择地刷新替换元件。 提供其他记忆，系统和方法。

公开(公告)号：US07965570B2

公开(公告)日：2011-06-21

申请号：US12901319

申请日：2010-10-08

申请人： Alan J. Wilson ,  Victor Wong ,  Jeffrey P. Wright

发明人： Alan J. Wilson ,  Victor Wong ,  Jeffrey P. Wright

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/1078 ,  G11C7/109

摘要： Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed.

摘要翻译： 公开了存储器，预充电控制电路，控制方法和使用方法，包括用于具有至少一个存储器组的存储器的预充电控制电路。 一个这样的控制电路包括至少一个预充电预处理器电路。 预充电预处理器电路耦合到相应的存储体组，并且被配置为防止存储器的预充电，直到执行发送到相应存储器组的缓冲写入命令完成为止。

公开(公告)号：US20090281908A1

公开(公告)日：2009-11-12

申请号：US12324084

申请日：2008-11-26

申请人： Victor Wong

发明人： Victor Wong

IPC分类号： G06Q30/00 ,  G06Q50/00

CPC分类号： H04N21/8113 ,  G06Q30/06 ,  G06Q30/0601 ,  G10H1/0025 ,  G10H2210/125 ,  G11B20/00086 ,  G11B20/00847 ,  G11B27/034 ,  G11B27/34 ,  H04N7/173 ,  H04N21/2543 ,  H04N21/47205

摘要： The present invention provides a system for purchasing music in integrated songs or divided into manipulatable components and then create new works with these components in unique productions and then release and distribute such music in either integrated or non integrated form stored with information that tracks the relative royalty characteristics of the stems/components of the song for later accounting and distribution of royalties to the owners of the song/song components/stems based on the purchase reproduction and resale of the components/stems/songs.

摘要翻译： 本发明提供了一种用于以综合歌曲购买音乐或分为可操纵部件的系统，然后以独特的制作方式与这些组件一起创建新作品，然后以集成或非集成形式发布和分发这样的音乐，该音乐与跟踪相关版权的信息一起存储 歌曲的部分/组成部分的特征，用于根据购买复制和转售组件/歌曲/歌曲，随后将歌曲/歌曲组成部分/歌曲的所有者会计和分发版税。

公开(公告)号：US20060245231A1

公开(公告)日：2006-11-02

申请号：US11476744

申请日：2006-06-29

申请人： J. Thompson ,  Jeffrey Wright ,  Victor Wong ,  Jim Cullum

发明人： J. Thompson ,  Jeffrey Wright ,  Victor Wong ,  Jim Cullum

IPC分类号： G11C5/06

CPC分类号： G11C7/1066 ,  G11C5/025 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C8/12 ,  G11C11/4085 ,  G11C11/4093

摘要： A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

摘要翻译： DDR SDRAM，其中单向行逻辑与单个存储器阵列相关联并连接到单个存储器阵列，而不是与多个存储器阵列相关联并连接到多个存储器阵列。 单向行逻辑位于其关联阵列的外围，但不在两个阵列之间的喉部区域内。 行逻辑的位置允许喉部区域包括更多的双向IO电路和服务两个阵列的信号线，这增加了SDRAM的性能。 此外，存储器阵列和IO电路采用单独的功率总线。 这可以防止阵列的噪声影响喉部区域的IO电路和信号线，反之亦然。

公开(公告)号：US07082064B2

公开(公告)日：2006-07-25

申请号：US10766004

申请日：2004-01-29

申请人： Mehul Nagrani ,  Victor Wong ,  Jeffrey P. Wright

发明人： Mehul Nagrani ,  Victor Wong ,  Jeffrey P. Wright

IPC分类号： G11C7/00

CPC分类号： G11C7/08

摘要： A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.

摘要翻译： 一种具有降低功耗的DRAM电路，在某些情况下，存储器阵列存取速度更快。 与阈值电容/长度相比，根据其电容/长度来感测连接到存储器阵列的输入/输出线。 比阈值更短或更低电容性的输入/输出线比比阈值更长，更容性的输入/输出线被感测得更早。 由于更短的输入/输出线路被更快地感测到，所以它们需要更少的功率并且可以更快地访问。

公开(公告)号：US20050270058A1

公开(公告)日：2005-12-08

申请号：US11200372

申请日：2005-08-09

申请人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph Sher ,  David Siek ,  Huy Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R31/26 ,  G01R31/30 ,  G11C5/14 ,  G11C29/02 ,  G11C29/12

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

摘要翻译： 用于产生用于封装的集成电路存储器件的内部电压的电压产生电路是可控的，以提供用于存储器件测试的电压的增量调节。 电压产生电路允许通过常规测试功能在执行标准中通过施加测试信号来外部控制存储器件的内部产生的电压，例如衬底电压Vbb，DVC 2电压和泵浦电压Vccp。 诸如静态刷新测试，逻辑1s和0s边缘测试等设备测试等，用于封装的存储器件。 此外，提供了包括可编程逻辑器件（例如抗熔丝）的可编程电路，其可编程以将电压维持在其调节幅度。

公开(公告)号：US6144593A

公开(公告)日：2000-11-07

申请号：US387650

申请日：1999-09-01

申请人： Timothy B. Cowles ,  Victor Wong ,  James S. Cullum ,  Jeffrey P. Wright

发明人： Timothy B. Cowles ,  Victor Wong ,  James S. Cullum ,  Jeffrey P. Wright

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A semiconductor memory device including a memory-cell array divided into a plurality of memory sub-arrays that are arranged into rows and columns of memory cells. Each of the sub-arrays have a limited number of redundant rows and columns to repair defective memory cells. The redundant memory of at least two memory sub-arrays are coupled to an I/O line through a respective isolation circuit. A control circuit coupled to the isolation circuits selectively couples the redundant memory of the sub-arrays to the I/O line. Coupling the redundant memory of multiple sub-arrays facilitates using the redundant memory of one sub-array to repair the defective memory cells in other sub-arrays also coupled to the I/O line, when the redundant memory primarily associated with the other sub-arrays have been depleted.

摘要翻译： 一种半导体存储器件，包括被划分成存储器单元的行和列的多个存储器子阵列的存储单元阵列。 每个子阵列具有有限数量的冗余行和列来修复有缺陷的存储单元。 至少两个存储器子阵列的冗余存储器通过相应的隔离电路耦合到I / O线。 耦合到隔离电路的控制电路选择性地将子阵列的冗余存储器耦合到I / O线。 耦合多个子阵列的冗余存储器有助于使用一个子阵列的冗余存储器来修复也耦合到I / O线的其他子阵列中的有缺陷的存储器单元，当主要与其他子阵列相关联的冗余存储器时， 阵列已经耗尽。