公开(公告)号：US20230352850A1

公开(公告)日：2023-11-02

申请号：US18309720

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Singh Phull Bakshi ,  Sylvester Ankamah-Kusi ,  Juan Herbsommer ,  Aditya Nitin Jogalekar

IPC: H01Q21/00 ,  H01Q1/22

CPC classification number: H01Q21/005 ,  H01Q1/2283

Abstract: An example microelectronic device package includes: a multilayer package substrate including a slotted waveguide antenna and having routing conductors, the multilayer package substrate having a device side surface and an opposing board side surface; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to slotted waveguide antenna by the routing conductors; and mold compound covering the semiconductor die, and a portion of the multilayer package substrate.

公开(公告)号：US20240313404A1

公开(公告)日：2024-09-19

申请号：US18429140

申请日：2024-01-31

Applicant: Texas Instruments Incorporated

Inventor： Harshpreet Singh Phull Bakshi ,  Rajen Manicon Murugan ,  Sylvester Ankamah-Kusi

IPC: H01Q9/04 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q1/42

CPC classification number: H01Q9/0407 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q1/422

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate has first, second, and third levels including respective dielectric layers and conductive features, the first level including a first trace layer with an antenna and a first via layer with a portion of a ground wall laterally spaced outward from and surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall, the semiconductor die attached to the first level of the multilevel package substrate, and the package structure including a molding compound enclosing the semiconductor die and extending on a side of the antenna, where the package structure mold compound maters and thickness can be tuned for improved performance.

公开(公告)号：US20240213185A1

公开(公告)日：2024-06-27

申请号：US18146886

申请日：2022-12-27

Applicant: Texas Instruments Incorporated

Inventor： Aditya Nitin Jogalekar ,  Harshpreet Singh Phull Bakshi ,  Rajen Manicon Murugan ,  Sylvester Ankamah-Kusi

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01P3/00 ,  H01P3/12 ,  H01P5/107 ,  H01P11/00

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01P3/003 ,  H01P3/121 ,  H01P5/107 ,  H01P11/002 ,  H01P11/003 ,  H01L2223/6633

Abstract: An electronic device includes a multilevel package substrate with a horizontal substrate integrated waveguide (SIW) with a channel, a vertical SIW with an opening, a grounded coplanar waveguide (GCPW), a first transition between the horizontal SIW and the GCPW, and a second transition between the horizontal and vertical SIWs, as well as a semiconductor die having conductive structures coupled to a signal trace and a ground trace of the GCPW, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.

公开(公告)号：US20240021971A1

公开(公告)日：2024-01-18

申请号：US18353074

申请日：2023-07-15

Applicant: Texas Instruments Incorporated

Inventor： Aditya Nitin Jogalekar ,  Harshpreet Singh Phull Bakshi ,  Rajen Murugan ,  Sylvester Ankamah-Kusi

IPC: H01P5/107 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01Q1/22

CPC classification number: H01P5/107 ,  H01L23/66 ,  H05K1/024 ,  H05K1/112 ,  H05K3/4644 ,  H01Q1/2283 ,  H05K1/0243 ,  H01L2223/6633 ,  H05K2201/10098

Abstract: An example device includes: a multilayer build-up package substrate including trace conductor layers spaced from one another by dielectric material, and further including connection conductor layers coupling portions of the trace conductor layers through dielectric material, the multilayer build-up package substrate having a device side surface with one of the trace conductor layers and an opposing board side surface with one of the connection conductor layers; and a waveguide transition formed from the multilayer build-up package substrate, the waveguide transition having an input port formed from the connection conductor layer on the board side surface, and having at least two sub-transitions spaced laterally from one another, the at least two sub-transitions to couple a signal from the input port through the trace conductor layers and the connection conductor layers to a coplanar waveguide formed from the trace conductor layer on the device side surface.