公开(公告)号：US20110090605A1

公开(公告)日：2011-04-21

申请号：US12977624

申请日：2010-12-23

Applicant: Takayasu ITO ,  Mitsuru Hiraki ,  Koichi Ashiga

Inventor： Takayasu ITO ,  Mitsuru Hiraki ,  Koichi Ashiga

IPC: H02H3/20

CPC classification number: H01L23/50 ,  H01L23/60 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0266 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2924/01029 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/00 ,  H02M3/07 ,  H02M3/157 ,  H01L2924/00

Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.

Abstract translation: 形成在半导体芯片上的集成电路包括用于降低外部提供的电源电压以产生内部电源电压的电压调节器，以及基于内部电源电压工作的内部电路。 电压调节器被放置在缓冲器和保护元件的区域中用于输入/输出信号和电源电压，使得由于电压调节器的片上提供而导致的开销面积被最小化。 内部电源电压通过环形主电源线分配到内部电路，电极焊盘用于连接外部电容器，用于稳定其上提供的内部电源电压，从而内部电源电压稳定，功耗 集成电路最小化。

公开(公告)号：US20080228414A1

公开(公告)日：2008-09-18

申请号：US12122715

申请日：2008-05-18

Applicant: Takayasu ITO ,  Mitsuru Hiraki ,  Masashi Horiguchi ,  Toyohiro Shimogawa

Inventor： Takayasu ITO ,  Mitsuru Hiraki ,  Masashi Horiguchi ,  Toyohiro Shimogawa

IPC: G06F19/00

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: The present invention provides a semiconductor device capable of realizing power saving and improvement in reliability or reduction in area. A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is shut down. Voltage of the internal power supply in which power is shut down is generated from voltage of an external power supply by using a regulator circuit. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When the power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, the increased voltage of the internal power supply is determined by the internal voltage determining circuit, operation of a circuit block is started, and the switch is turned on.

Abstract translation: 本发明提供一种半导体装置，其能够实现节电，提高可靠性或减小面积。 一种半导体装置，包括：连接不断电的内部电源的电源开关和断电的内部电源; 以及用于确定电源关闭的内部电源的电压的内部电压确定电路。 通过使用调节电路从外部电源的电压产生关闭电源的内部电源的电压。 当内部电源的电源中断时，电源开关关闭，调节器电路关闭，调节器电路的输出短路到地电位。 当恢复内部电源的电源时，调节器电路接通，短路被取消，内部电源的增加的电压由内部电压确定电路确定，电路块的操作开始，开关 打开

公开(公告)号：US20100327841A1

公开(公告)日：2010-12-30

申请号：US12796033

申请日：2010-06-08

Applicant: Takayasu ITO ,  Mitsuru HIRAKI ,  Masashi HORIGUCHI

Inventor： Takayasu ITO ,  Mitsuru HIRAKI ,  Masashi HORIGUCHI

IPC: G05F3/16

CPC classification number: G11C5/147

Abstract: The present invention provides a technique for reducing current consumption in a reference voltage forming circuit without a significant increase in area while suppressing considerable degradative difference in reference voltage accuracy between a normal operation mode and a standby mode. In the standby mode, by using a clock signal fed from an oscillator circuit, the frequency-division control circuit produces an enable signal VREFON for determining ON/OFF states of the reference voltage generator circuit, the reference voltage forming circuit, and the capacitance charging regulator, and also produces a sampling/holding signal CHOLDSW for performing control so that a holding capacitor CH in a holding capacitance circuit is charged during an ON period of the reference voltage generator circuit, the reference voltage forming circuit, and the capacitance charging regulator, and so that any paths other than a leak current path are made unavailable to the holding capacitor CH during an OFF period thereof. Current consumption can be reduced significantly by intermittently turning ON/OFF the reference voltage generator circuit, the reference voltage forming circuit, and the capacitance charging regulator, each of which would otherwise consume a relatively large amount of current for operation thereof.

Abstract translation: 本发明提供一种降低参考电压形成电路中的电流消耗而不显着增加面积的技术，同时抑制正常操作模式和待机模式之间参考电压精度的相当大的降低差异。 在待机模式中，通过使用从振荡电路馈送的时钟信号，分频控制电路产生用于确定参考电压发生器电路，参考电压形成电路和电容充电的ON / OFF状态的使能信号VREFON 并且还产生用于执行控制的采样/保持信号CHOLDSW，使得在参考电压发生器电路，参考电压形成电路和电容充电调节器的导通时段期间，保持电容电路中的保持电容器CH被充电， 并且使得除了漏电流路径之外的任何路径在保持电容器CH的OFF周期期间使其不可用。 通过间歇地打开/关闭参考电压发生器电路，参考电压形成电路和电容充电调节器，可以大大减少电流消耗，否则每个电容器将消耗相对大量的用于其操作的电流。

公开(公告)号：US20100019835A1

公开(公告)日：2010-01-28

申请号：US12475867

申请日：2009-06-01

Applicant: Naoya ARISAKA ,  Takayasu ITO

Inventor： Naoya ARISAKA ,  Takayasu ITO

IPC: G05F3/08

CPC classification number: H01L27/0207 ,  G11C16/30 ,  H01L23/4824 ,  H01L27/0218 ,  H01L27/11526 ,  H01L27/11573 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/0002 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.

Abstract translation: 一种半导体集成电路器件，其基本上减小了由调节器产生的电源电压的下降，并确保以高效率和高精度稳定地供应电源电压。 在该装置中，存储器电源包括多个晶体管和误差放大器。 在晶体管中，源极焊盘和漏极焊盘沿芯片的外围区域中的半导体芯片的一个边缘交替布置成一行。 晶体管栅极与交替布置的源极焊盘和漏极焊盘平行地形成（使得栅极的纵向方向平行于源极焊盘和漏极焊盘的布置方向）。 因此，连接到排水沟和源的布线长度缩短，薄层电阻降低。

公开(公告)号：US20120265473A1

公开(公告)日：2012-10-18

申请号：US13439289

申请日：2012-04-04

Applicant: Naoya ARISAKA ,  Takayasu ITO ,  Masashi HORIGUCHI

Inventor： Naoya ARISAKA ,  Takayasu ITO ,  Masashi HORIGUCHI

IPC: G06F19/00 ,  G01K15/00

CPC classification number: G01K15/005 ,  G01K7/01 ,  G05F3/30

Abstract: Improvement in the accuracy of a temperature sensor is aimed at, suppressing the number of the test temperature in a test process. The semiconductor device comprises a coefficient calculation unit which calculates up to the N-th order coefficient (N is an integer equal to or greater than one) of a correction function as an N-th order approximation of a characteristic function indicating correspondence relation of temperature data measured by a temperature sensor unit and temperature, based on N+1 pieces of the temperature data including a theoretical value at a predetermined temperature in the characteristic function and N measured values of the temperature data measured by the temperature sensor unit at N points of temperature; and a correction operation unit which generates data including information on temperature, by performing calculation using the correction function to which the coefficients calculated are applied, based on temperature data measured by the temperature sensor unit.

Abstract translation: 提高温度传感器的精度旨在在测试过程中抑制测试温度的数量。 半导体器件包括系数计算单元，其计算校正函数的N阶系数（N是等于或大于1的整数）作为指示温度的对应关系的特征函数的N阶近似 基于包括特征函数中的预定温度下的理论值的N + 1个温度数据和由温度传感器单元在N点测量的温度数据的N个测量值，由温度传感器单元和温度测量的数据 温度; 以及校正操作单元，其基于由温度传感器单元测量的温度数据，通过使用所计算的系数的校正函数进行计算，生成包括关于温度的信息的数据。

公开(公告)号：US20090295458A1

公开(公告)日：2009-12-03

申请号：US12422854

申请日：2009-04-13

Applicant: Tadashi KAMEYAMA ,  Takayasu ITO ,  Seiichi SAITO ,  Koji SATO

Inventor： Tadashi KAMEYAMA ,  Takayasu ITO ,  Seiichi SAITO ,  Koji SATO

IPC: H01L35/00

CPC classification number: G05F3/30 ,  G05F3/227

Abstract: The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.

Abstract translation: 提供了半导体集成电路，其中可以进行外部温度控制或温度监视，几乎不受安装半导体集成电路的系统板的噪声的影响。 半导体集成电路包括检测芯片温度的温度检测电路和流过大的工作电流的功能模块。 提供工作电压的外部端子和提供接地电压的外部端子耦合到功能模块。 温度检测电路产生温度检测信号和参考信号。 参考信号和温度检测信号分别经由第一外部输出端子和第二外部输出端子被引出到半导体集成电路的外部，并且被提供给具有电路类型的外部温度控制/监视电路 的差分放大电路。

公开(公告)号：US20110090001A1

公开(公告)日：2011-04-21

申请号：US12980140

申请日：2010-12-28

Applicant: Naoya ARISAKA ,  Takayasu ITO

Inventor： Naoya ARISAKA ,  Takayasu ITO

IPC: G05F1/59

CPC classification number: H01L27/0207 ,  G11C16/30 ,  H01L23/4824 ,  H01L27/0218 ,  H01L27/11526 ,  H01L27/11573 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/0002 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.

Abstract translation: 一种半导体集成电路器件，其基本上减小了由调节器产生的电源电压的下降，并确保以高效率和高精度稳定地供应电源电压。 在该装置中，存储器电源包括多个晶体管和误差放大器。 在晶体管中，源极焊盘和漏极焊盘沿芯片的外围区域中的半导体芯片的一个边缘交替布置成一行。 晶体管栅极与交替布置的源极焊盘和漏极焊盘平行地形成（使得栅极的纵向方向平行于源极焊盘和漏极焊盘的布置方向）。 因此，连接到排水管和源的布线长度缩短，薄层电阻降低。