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677 条记录 (耗时 0.037 秒)

    SEPP-Based deflection control circuit
    2.
    发明授权
    SEPP-Based deflection control circuit 失效
    基于SEPP的偏转控制电路

    公开(公告)号：US4409613A

    公开(公告)日：1983-10-11

    申请号：US354307

    申请日：1982-03-03

    申请人： Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji ,  Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji

    发明人： Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji ,  Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji

    IPC分类号： H04N3/16 ,  H04N3/22 ,  H04N9/09 ,  H04N9/093

    CPC分类号： H04N9/09

    摘要： Deflection control apparatus for registering the electron beam, rasters of electrostatic-deflection pick-up tubes of a three-tube color television camera includes a compensating voltage generator with inputs connected to receive horizontal and vertical sawtooth deflection signals provided from a deflection signal generator, and outputs providing compensating voltages to adjust for size, skew, and rotation. A combining circuit is provided to add the deflecting signals to the respective compensating voltages to generate adjusted compensating voltages for application to respective electrostatic deflection plates of certain ones of the tubes. For each adjusted deflecting signal, the combining circuit includes a transistor circuit having an input electrode coupled to receive the associated compensating voltage and an output electrode connected through a load resistor to an output of the deflecting signal generator. A pair of SEPP-arranged transistors are provided with their bases connected to the output electrode of the transistor circuit and with their emitters coupled together, through like-value emitter resistors, to a respective deflection plate of one of the tubes. The SEPP-configured transistors permit a high impedance to be presented to the deflection signal generator to minimize the power consumption thereof, and a low resistance to be presented to the deflection plates, to keep the latter from undesirably integrating the deflection sawtooth voltages.

    摘要翻译： 用于对电子束进行配准的偏转控制装置，三管彩色电视摄像机的静电偏转拾取管的光栅包括：补偿电压发生器，具有连接的输入端，用于接收从偏转信号发生器提供的水平和垂直锯齿波偏转信号;以及 输出提供补偿电压以调整大小，偏斜和旋转。 提供组合电路以将偏转信号添加到相应的补偿电压以产生用于施加到某些管的各个静电偏转板的调整的补偿电压。 对于每个经调整的偏转信号，组合电路包括晶体管电路，其具有耦合以接收相关联的补偿电压的输入电极和通过负载电阻器连接到偏转信号发生器的输出的输出电极。 一对SEPP布置的晶体管被​​设置有它们的基极连接到晶体管电路的输出电极，并且它们的发射极通过同值发射极电阻耦合到一个管的相应的偏转板上。 SEPP配置的晶体管允许将高阻抗呈现给偏转信号发生器以最小化其功率消耗，以及将低电阻提供给偏转板，以防止偏转锯齿波电压的不期望的积分。

    ELECTRONIC DEVICE
    5.
    发明申请
    ELECTRONIC DEVICE 审中-公开
    电子设备

    公开(公告)号：US20130223025A1

    公开(公告)日：2013-08-29

    申请号：US13588100

    申请日：2012-08-17

    申请人： Tadaomi Fujieda ,  Takashi Nakamura

    发明人： Tadaomi Fujieda ,  Takashi Nakamura

    IPC分类号： H05K7/02

    CPC分类号： H05K7/02 ,  G06F1/1656

    摘要： Provided is an electronic device including a housing, at least a part of which has conductive properties; a substrate on which a heating element is mounted and which has a ground pattern; and a spacer which is located between the housing and the ground pattern and which includes a main body portion having heat insulating properties and a conductive portion which is in contact with the ground pattern and the housing and which conducts current between the ground pattern and the housing.

    摘要翻译： 提供一种电子设备，其包括壳体，其至少一部分具有导电性能; 其上安装有加热元件并具有接地图案的基板; 以及间隔件，其位于壳体和接地图案之间，并且包括具有绝热性能的主体部分和与接地图案和壳体接触的导电部分并且在接地图案和壳体之间传导电流的间隔件 。

    IMAGE PROCESSING APPARATUS AND INFORMATION SETTING SYSTEM
    7.
    发明申请
    IMAGE PROCESSING APPARATUS AND INFORMATION SETTING SYSTEM 有权
    图像处理设备和信息设置系统

    公开(公告)号：US20130063761A1

    公开(公告)日：2013-03-14

    申请号：US13602572

    申请日：2012-09-04

    申请人： Hiroki Uchibori ,  Kei Nakabayashi ,  Takashi Nakamura ,  Osamu Kizaki ,  Sachiko Takeuchi

    发明人： Hiroki Uchibori ,  Kei Nakabayashi ,  Takashi Nakamura ,  Osamu Kizaki ,  Sachiko Takeuchi

    IPC分类号： G06K15/02

    CPC分类号： G06F3/1285 ,  G06F3/1203 ,  G06F3/1231 ,  G06F9/445 ,  H04N1/00127 ,  H04N1/00973

    摘要： An image processing apparatus includes a storing unit that stores setting information for operating the image processing apparatus; and an updating control unit that sends a request for obtaining predetermined differentiated setting information, which is a part of a set of setting information stored in a data processing apparatus in a differentiated manner in accordance with a predetermined differentiating criterion, to the data processing apparatus via a network, obtains the predetermined differentiated setting information from the data processing apparatus via the network and controls to update the setting information stored in the storing unit by the obtained predetermined differentiated setting information.

    摘要翻译： 图像处理装置包括：存储单元，存储用于操作图像处理装置的设置信息; 以及更新控制单元，其根据预定的微分准则向数据处理设备发送作为数据处理设备中存储的一组设置信息的一部分的预定差分设置信息的请求，经过 网络，经由网络从数据处理装置获得预定的差异化设置信息，并且控制通过获得的预定差分设置信息来更新存储在存储单元中的设置信息。

    Memory test apparatus and testing method
    8.
    发明授权
    Memory test apparatus and testing method 有权
    记忆测试仪器及测试方法

    公开(公告)号：US08345496B2

    公开(公告)日：2013-01-01

    申请号：US12990983

    申请日：2009-05-07

    申请人： Takashi Nakamura

    发明人： Takashi Nakamura

    IPC分类号： G11C29/00

    CPC分类号： G11C29/56 ,  G11C11/401 ,  G11C29/50016 ,  G11C29/56012

    摘要： A refresh control circuit receives an interrupt signal, which is a request to refresh DRAM (Dynamic Random Access Memory) and which is asserted at predetermined timings. The refresh control circuit counts the number of times the interrupt signal is asserted, and asserts an interrupt subroutine start signal, which is an instruction to refresh the DRAM, in an idle state in which the DRAM is accessible from an external circuit, for a number of times that is equal to the number of times thus counted. When the interrupt subroutine start signal is asserted, a refresh circuit executes a predetermined interrupt subroutine, and supplies a refresh pattern to the DRAM.

    摘要翻译： 刷新控制电路接收中断信号，该中断信号是刷新DRAM（动态随机存取存储器）的请求，并且以预定的定时被断言。 刷新控制电路对中断信号被断言的次数进行计数，并且在可从外部电路访问DRAM的空闲状态下断言作为刷新DRAM的指令的中断子程序开始信号，数量 的次数等于这样计算的次数。 当中断子程序启动信号被断言时，刷新电路执行预定的中断子程序，并向DRAM提供刷新模式。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    9.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20120319738A1

    公开(公告)日：2012-12-20

    申请号：US13579766

    申请日：2010-02-19

    申请人： Takashi Nakamura ,  Kosuke Yayama

    发明人： Takashi Nakamura ,  Kosuke Yayama

    IPC分类号： H03L7/00

    CPC分类号： H03L1/022 ,  H03L7/00

    摘要： A frequency-voltage converting circuit 13 is composed of a switch unit including switches SW1 and SW2, electrostatic capacitive elements C and C10 to C13, and switches CSW0 to CSW3. The electrostatic capacitive elements C10 to C13 are composed of elements having mutually different absolute values of capacitance and are provided so as to cover a frequency range intended by a designer. The electrostatic capacitance values are weighted by, for example, 2. The electrostatic capacitive elements C11 to C13 are selected by, for example, the switches CSW0 to CSW3 based on 4-bit frequency adjustment control signals SELC0 to SELC3, thereby carrying out frequency switching.

    摘要翻译： 频率电压转换电路13由包括开关SW1和SW2，静电电容元件C和C10至C13的开关单元，以及开关CSW0至CSW3组成。 静电电容元件C10至C13由具有相互不同的电容绝对值的元件组成，并且被设置为覆盖由设计者预期的频率范围。 静电电容值通过例如2进行加权。静电电容元件C11至C13通过例如基于4位频率调整控制信号SELC0至SELC3的开关CSW0至CSW3来选择，从而进行频率切换 。

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120161868A1

    公开(公告)日：2012-06-28

    申请号：US13333448

    申请日：2011-12-21

    申请人： Kosuke YAYAMA ,  Takashi Nakamura

    发明人： Kosuke YAYAMA ,  Takashi Nakamura

    IPC分类号： H03F3/45

    CPC分类号： H03L7/00 ,  H03K3/0231 ,  H03L1/00 ,  H03L1/022

    摘要： A clock signal capable of changing the frequency in a wide range and with high resolution is generated.An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.

    摘要翻译： 产生能够在宽范围内以高分辨率改变频率的时钟信号。 运算放大器AMP1经受反馈控制，使得正输入部分的电压等于负输入部分的电压。 电路节点fbck的电压等于参考电压VREFI。 解码器DEC解码控制信号CNT7和CNT6，并导通晶体管T2至T5中的一个。 该配置提供反馈控制，使得电路节点fbck的电压等于参考电压VREFI。 这显着地降低了晶体管T2至T5的导通电阻并防止了频率精度的降低。