A refresh control circuit receives an interrupt signal, which is a request to refresh DRAM (Dynamic Random Access Memory) and which is asserted at predetermined timings. The refresh control circuit counts the number of times the interrupt signal is asserted, and asserts an interrupt subroutine start signal, which is an instruction to refresh the DRAM, in an idle state in which the DRAM is accessible from an external circuit, for a number of times that is equal to the number of times thus counted. When the interrupt subroutine start signal is asserted, a refresh circuit executes a predetermined interrupt subroutine, and supplies a refresh pattern to the DRAM.