公开(公告)号：US07245859B2

公开(公告)日：2007-07-17

申请号：US11154802

申请日：2005-06-17

Applicant: Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

Inventor： Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

IPC: G03G15/01

CPC classification number: G03G15/0152 ,  G03G15/0121 ,  G03G15/0173 ,  G03G21/1832 ,  G03G2221/1884

Abstract: An image-forming apparatus includes a rotary developing device including a casing having absolute value of the surface potential of not larger than 300 V.

Abstract translation: 图像形成装置包括旋转显影装置，其包括表面电位绝对值不大于300V的外壳。

公开(公告)号：US20060285884A1

公开(公告)日：2006-12-21

申请号：US11154802

申请日：2005-06-17

Applicant: Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

Inventor： Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

IPC: G03G15/01

CPC classification number: G03G15/0152 ,  G03G15/0121 ,  G03G15/0173 ,  G03G21/1832 ,  G03G2221/1884

Abstract: Disclosed is an image-forming apparatus comprising a rotary developing device including a casing having absolute value of the surface potential of not larger than 300 V.

Abstract translation: 公开了一种图像形成装置，包括具有表面电位绝对值不大于300V的壳体的旋转显影装置。

公开(公告)号：US07376372B2

公开(公告)日：2008-05-20

申请号：US11822196

申请日：2007-07-03

Applicant: Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

Inventor： Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

IPC: G03G15/01 ,  G03G15/08

CPC classification number: G03G15/0152 ,  G03G15/0121 ,  G03G15/0173 ,  G03G21/1832 ,  G03G2221/1884

Abstract: An image-forming apparatus includes a rotary developing device including a casing having absolute value of the surface potential of not larger than 300 V.

Abstract translation: 图像形成装置包括旋转显影装置，其包括表面电位绝对值不大于300V的外壳。

公开(公告)号：US20070253741A1

公开(公告)日：2007-11-01

申请号：US11822196

申请日：2007-07-03

Applicant: Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

Inventor： Takahito Kabai ,  Satoshi Itaya ,  Mitsuhisa Kato

IPC: G03G15/01

CPC classification number: G03G15/0152 ,  G03G15/0121 ,  G03G15/0173 ,  G03G21/1832 ,  G03G2221/1884

Abstract: An image-forming apparatus includes a rotary developing device including a casing having absolute value of the surface potential of not larger than 300 V.

Abstract translation: 图像形成装置包括旋转显影装置，其包括表面电位绝对值不大于300V的外壳。

公开(公告)号：US20110084385A1

公开(公告)日：2011-04-14

申请号：US12923789

申请日：2010-10-07

Applicant: Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

Inventor： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

IPC: H01L23/485

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

Abstract translation: 半导体器件包括多个核心芯片和控制芯片芯片的接口芯片。 芯片芯片和接口芯片中的每一个都包括穿透半导体衬底的多个穿过硅通孔和分别连接到通孔硅通孔的多个焊盘。 贯通硅通孔包括供电电源电位或接地电位的电源系统的贯穿硅通孔，以及供给各种信号的信号系统的通孔硅通孔。 在焊盘中，连接到电源系统的贯穿硅通孔的焊盘的至少一个尺寸大于连接到信号系统的通过硅通孔的焊盘的尺寸。 因此，可以确保更大的寄生电容。

公开(公告)号：US07694245B2

公开(公告)日：2010-04-06

申请号：US11710965

申请日：2007-02-27

Applicant: Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

Inventor： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L23/50 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

Abstract translation: 公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。 考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。 考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。 选择第一和第二目标变量之一作为主要目标变量。 比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

公开(公告)号：US20090327981A1

公开(公告)日：2009-12-31

申请号：US12457930

申请日：2009-06-25

Applicant: Satoshi Nakamura ,  Tsutomu Hara ,  Mitsuaki Katagiri ,  Yukitoshi Hirose ,  Satoshi Itaya ,  Ken Iwakura

Inventor： Satoshi Nakamura ,  Tsutomu Hara ,  Mitsuaki Katagiri ,  Yukitoshi Hirose ,  Satoshi Itaya ,  Ken Iwakura

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/78 ,  H05K1/181 ,  H05K3/0005

Abstract: Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.

Abstract translation: 获取校正电路模型，用于校正在电路板上安装时变化的电特性参数。 校正电路模型被添加到单独的模型中，该模型表示隔离的单独的半导体器件以产生表示板安装状态的半导体器件的半导体器件模型。 表示调整对象系统的等效电路模型连接到所创建的半导体器件模型，并且基于与等效电路模型相连接的半导体器件模型，与调整对象系统相关的调整对象值为 计算。 将这些调整对象值与预先确定的限制值进行比较，并且基于比较结果，确定调整对象系统的设计指南。

公开(公告)号：US20110311257A1

公开(公告)日：2011-12-22

申请号：US13164095

申请日：2011-06-20

Applicant: Taizo Nozawa ,  Yukio Futamata ,  Noboru Furuyama ,  Satoshi Itaya ,  Hiroshi Katakura ,  Setsuo Takada

Inventor： Taizo Nozawa ,  Yukio Futamata ,  Noboru Furuyama ,  Satoshi Itaya ,  Hiroshi Katakura ,  Setsuo Takada

IPC: G03G15/20

CPC classification number: G03G15/2078 ,  G03G15/2039

Abstract: An embodiment provides an image forming apparatus including: a job acquiring unit that acquires an image forming job that gives instructions for performing forming of an image; an image forming process control unit that controls performance of the image forming job that the job acquiring unit acquires; a temperature information acquiring unit that acquires information showing temperature of the heating rotary body; a determining unit that determines whether the temperature of the heating rotary body which is acquired by the temperature information acquiring unit is equal to or higher than a predetermined stand-by temperature set as a temperature in a stand-by state that stands by to perform the image forming process, when the image forming process is completed, based on the image forming job by the image forming process control unit; and a fixing device control unit, which controls the fixing device, performs a first stand-by control process that increases the temperature of the heating rotary body to the stand-by temperature by heating the heating rotary body with the heating member while rotating the heating rotary body with the heating rotary body and the pressing body in contact, when the determining unit determines that the temperature of the heating rotary body is lower than the stand-by temperature. Further, the fixing device control unit stops the rotation of the heating rotary body and performs a second stand-by control process that makes the fixing device stand by, without heating the heating rotary body with the heating member, when the determining unit determines that the temperature of the heating rotary body is the stand-by temperature or higher.

Abstract translation: 实施例提供了一种图像形成装置，包括：作业获取单元，其获取给出用于执行图像形成的指令的图像形成作业; 图像形成处理控制单元，其控制作业获取单元获取的图像形成作业的性能; 温度信息获取单元，其获取表示所述加热旋转体的温度的信息; 确定单元，其确定由所述温度信息获取单元获取的所述加热旋转体的温度是否等于或高于设置为待机状态下的待执行状态的预定待机温度 图像形成处理，当图像形成处理完成时，基于图像形成处理控制单元的图像形成作业; 以及控制定影装置的定影装置控制单元，进行第一待机控制处理，其通过在加热部件的同时加热加热旋转体而使加热旋转体的温度升高到待机温度 当确定单元确定加热旋转体的温度低于待机温度时，加热旋转体的旋转体和压制体接触。 此外，定影装置控制单元停止加热旋转体的旋转，并且当确定单元确定了加热旋转体的旋转时，执行使定影装置待机的第二待机控制处理，而不加热加热旋转体， 加热旋转体的温度为待机温度或更高。

公开(公告)号：US20070204251A1

公开(公告)日：2007-08-30

申请号：US11710965

申请日：2007-02-27

Applicant: Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

Inventor： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H01L23/50 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

Abstract translation: 公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。 考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。 考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。 选择第一和第二目标变量之一作为主要目标变量。 比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

公开(公告)号：US08350389B2

公开(公告)日：2013-01-08

申请号：US12923789

申请日：2010-10-07

Applicant: Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

Inventor： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

Abstract translation: 半导体器件包括多个核心芯片和控制芯片芯片的接口芯片。 芯片芯片和接口芯片中的每一个都包括穿透半导体衬底的多个穿过硅通孔和分别连接到通孔硅通孔的多个焊盘。 贯通硅通孔包括供电电源电位或接地电位的电源系统的贯穿硅通孔，以及供给各种信号的信号系统的通孔硅通孔。 在焊盘中，连接到电源系统的贯穿硅通孔的焊盘的至少一个尺寸大于连接到信号系统的通过硅通孔的焊盘的尺寸。 因此，可以确保更大的寄生电容。