Receiver, transceiver, and mobile terminal device
    3.
    发明授权
    Receiver, transceiver, and mobile terminal device 失效
    接收机,收发器和移动终端设备

    公开(公告)号:US08238839B2

    公开(公告)日:2012-08-07

    申请号:US12732393

    申请日:2010-03-26

    IPC分类号: H04B1/40

    摘要: Variable operating currents are generated in relation to input signal power and output signal power and achieving both low noise and low power consumption. Emitter follower circuits are attached to output terminals of a frequency divider for generating a local signal. By adjusting the currents flowing through the emitter follower circuits, the amounts of currents flowing into mixers is adjusted. When the amounts of currents of local signals flowing into the mixers increases, the effect of noise suppression is expected. The amounts of the currents flowing through the emitter follower circuits is changed depending on the amplification factor of variable amplifiers.

    摘要翻译: 相对于输入信号功率和输出信号功率产生可变工作电流,并实现低噪声和低功耗。 发射器跟随器电路连接到分频器的输出端,用于产生本地信号。 通过调节流过射极跟随器电路的电流,调节流入混频器的电流量。 当流入混频器的本地信号的电流量增加时,预期噪声抑制的影响。 流过射极跟随器电路的电流量根据可变放大器的放大系数而改变。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号:US20100052795A1

    公开(公告)日:2010-03-04

    申请号:US12540248

    申请日:2009-08-12

    IPC分类号: H03L7/099

    摘要: The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2M−1. The capacitance values of the fine-tuning capacitor unit cells of the frequency fine-tuning variable capacitor array are also set in accordance with a binary weight 2N−1.

    摘要翻译: 本发明提供一种能够减少芯片占用面积并减少数字控制振荡器的控制增益的变化的半导体集成电路。 半导体集成电路配有数字控制振荡器。 数字控制振荡器包括振荡晶体管和谐振电路。 谐振电路包括电感,频率粗调可变电容器阵列和频率微调可变电容器阵列。 频率粗调可变电容器阵列包括多个粗调谐电容器单元。 频率微调可变电容器阵列包括多个微调电容器单元。 频率粗调可变电容器阵列的粗​​调电容器单元的电容值根据二进制权重2M-1来设定。 频率微调可变电容器阵列的微调电容器单元的电容值也根据二进制权重2N-1设定。

    Embedded structure circuit for VCO and regulator
    5.
    发明授权
    Embedded structure circuit for VCO and regulator 有权
    VCO和调节器的嵌入式结构电路

    公开(公告)号:US07336138B2

    公开(公告)日:2008-02-26

    申请号:US11412973

    申请日:2006-04-28

    IPC分类号: H03B5/12 H03L1/00

    摘要: An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.

    摘要翻译: 一种形成在单个半导体芯片中的振荡电路,其中第一电源电压被提供给第一电源端子,与第一电源电压不同的第二源极电压被提供给第二电源端子,电压调节器接收来自 第一电源端子输出源电压,电压控制振荡电路从电压调节器提供源电压,电流源电路连接到第二电源端子,电压调节器,压控振荡电路和 电流源电路串联插在第一和第二电源端子之间,并且从电压调节器提供给压控振荡电路的电流在电流源电路中流动。

    Oscillation circuit and a communication semiconductor integrated circuit
    6.
    发明授权
    Oscillation circuit and a communication semiconductor integrated circuit 失效
    振荡电路和通信半导体集成电路

    公开(公告)号:US06906596B2

    公开(公告)日:2005-06-14

    申请号:US10253922

    申请日:2002-09-25

    摘要: A voltage controlled LC resonance oscillation circuit has a plurality of capacitive elements connected to an output node. These capacitive elements are applied with voltages at opposing terminals for selecting an oscillating frequency band, so that the oscillating frequency band can be changed step by step in accordance with the selection voltage. The capacitive elements include at least one variable capacitive element such as a MOS capacitor, the capacitance of which is varied in accordance with a voltage applied thereto. The MOS capacitor is similar in structure to a MOS transistor. The variable capacitive element can be supplied at a terminal opposite to the output node with a voltage from a variable voltage source, for example, in place of the selection voltage. The voltage controlled LC resonance oscillation circuit can measure the output amplitude and oscillating frequency without affecting the characteristics thereof, and reduce the parasitic capacitance.

    摘要翻译: 电压控制LC谐振振荡电路具有连接到输出节点的多个电容元件。 这些电容元件在相对端子处施加电压以选择振荡频带,使得可以根据选择电压逐步改变振荡频带。 电容元件包括至少一个可变电容元件,例如MOS电容器,其电容根据施加到其上的电压而变化。 MOS电容器的结构类似于MOS晶体管。 可变电容元件可以在与输出节点相对的端子处具有来自可变电压源的电压,例如代替选择电压。 电压LC共振振荡电路可以测量输出幅度和振荡频率,而不影响其特性,并降低寄生电容。

    ADPLL circuit, semiconductor device, and portable information device
    7.
    发明授权
    ADPLL circuit, semiconductor device, and portable information device 有权
    ADPLL电路,半导体器件和便携式信息器件

    公开(公告)号:US08638142B2

    公开(公告)日:2014-01-28

    申请号:US13616449

    申请日:2012-09-14

    IPC分类号: H03L7/06

    摘要: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

    摘要翻译: 本发明提供了在ADPLL环境或靠近ADPLL环境的环境下的ABS精度改进手段,实现了ABS的加工时间缩短。 在ABS电路中的数字频率比较器中,准备用于存储从DPFD输出的DPE信号中的初始相位差的DFF。 在ABS操作开始之后,从DPFD输出的DPE信号被记录为将DPFD的内部电路中的初始相位差表示为DFF的信号。 之后,数字频率比较器通过使用从输入DPE信号中减去记录在DFF中的初始相位误差获得的信号来执行ABS,从而实现高速和稳定的ABS操作。

    Embedded structure circuit for VCO and regulator
    8.
    发明申请
    Embedded structure circuit for VCO and regulator 有权
    VCO和调节器的嵌入式结构电路

    公开(公告)号:US20070262825A1

    公开(公告)日:2007-11-15

    申请号:US11412973

    申请日:2006-04-28

    IPC分类号: H03L7/099

    摘要: An oscillation circuit formed in a single semiconductor chip, wherein a first source voltage is supplied to a first power supply terminal, a second source voltage different from the first source voltage is supplied to a second power supply terminal, a voltage regulator receives the voltage from the first power supply terminal and outputs a source voltage, a voltage controlled oscillation circuit is supplied with a source voltage from the voltage regulator, a current source circuit is connected to the second power supply terminal, the voltage regulator, the voltage controlled oscillation circuit and the current source circuit are inserted in series between the first and second power supply terminals, and the current supplied to the voltage controlled oscillation circuit from the voltage regulator flows in the current source circuit.

    摘要翻译: 一种形成在单个半导体芯片中的振荡电路,其中第一电源电压被提供给第一电源端子,与第一电源电压不同的第二源极电压被提供给第二电源端子,电压调节器接收来自 第一电源端子输出源电压,电压控制振荡电路从电压调节器提供源电压,电流源电路连接到第二电源端子,电压调节器,压控振荡电路和 电流源电路串联插在第一和第二电源端子之间,并且从电压调节器提供给压控振荡电路的电流在电流源电路中流动。

    ADPLL circuit, semiconductor device, and portable information device
    9.
    发明授权
    ADPLL circuit, semiconductor device, and portable information device 失效
    ADPLL电路,半导体器件和便携式信息器件

    公开(公告)号:US08299828B2

    公开(公告)日:2012-10-30

    申请号:US13463982

    申请日:2012-05-04

    IPC分类号: H03L7/06

    摘要: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

    摘要翻译: 本发明提供了在ADPLL环境或靠近ADPLL环境的环境下的ABS精度改进手段,实现了ABS的加工时间缩短。 在ABS电路中的数字频率比较器中,准备用于存储从DPFD输出的DPE信号中的初始相位差的DFF。 在ABS操作开始之后,从DPFD输出的DPE信号被记录为将DPFD的内部电路中的初始相位差表示为DFF的信号。 之后,数字频率比较器通过使用从输入DPE信号中减去记录在DFF中的初始相位误差获得的信号来执行ABS,从而实现高速和稳定的ABS操作。

    ADPLL circuit, semiconductor device, and portable information device

    公开(公告)号:US08207767B2

    公开(公告)日:2012-06-26

    申请号:US12955192

    申请日:2010-11-29

    IPC分类号: H03L7/06

    摘要: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.