公开(公告)号：US20230069737A1

公开(公告)日：2023-03-02

申请号：US17458610

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chung Chang ,  Ming-Che Ho ,  Hung-Jui Kuo

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L21/285 ,  H01L21/768

摘要： A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

公开(公告)号：US11901230B2

公开(公告)日：2024-02-13

申请号：US17460317

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chung Chang ,  Ming-Che Ho ,  Hung-Jui Kuo

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/10 ,  H01L23/498

CPC分类号： H01L21/76898 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76871 ,  H01L23/481 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2225/1041

摘要： Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

公开(公告)号：US20230065788A1

公开(公告)日：2023-03-02

申请号：US17460317

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chung Chang ,  Ming-Che Ho ,  Hung-Jui Kuo

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/10

摘要： Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

公开(公告)号：US20240128122A1

公开(公告)日：2024-04-18

申请号：US18395706

申请日：2023-12-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chung Chang ,  Ming-Che Ho ,  Hung-Jui Kuo

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L25/10

CPC分类号： H01L21/76898 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76871 ,  H01L23/481 ,  H01L25/105 ,  H01L23/49816 ,  H01L2225/1041

摘要： Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

公开(公告)号：US20240096849A1

公开(公告)日：2024-03-21

申请号：US18152141

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chung Chang ,  Ming-Che Ho ,  Hung-Jui Kuo

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L21/565 ,  H01L21/76829 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/24 ,  H01L23/49827 ,  H01L2224/16135 ,  H01L2224/2401

摘要： A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.

公开(公告)号：US20240047308A1

公开(公告)日：2024-02-08

申请号：US18482006

申请日：2023-10-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chung Chang ,  Ming-Che Ho ,  Hung-Jui Kuo

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/285 ,  H01L23/31

CPC分类号： H01L23/481 ,  H01L21/76879 ,  H01L21/2855 ,  H01L23/3157

摘要： A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

公开(公告)号：US11823981B2

公开(公告)日：2023-11-21

申请号：US17458610

申请日：2021-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Chung Chang ,  Ming-Che Ho ,  Hung-Jui Kuo

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/285 ,  H01L23/31

CPC分类号： H01L23/481 ,  H01L21/2855 ,  H01L21/76879 ,  H01L23/3157

摘要： A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.