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公开(公告)号：US20190146455A1
公开(公告)日：2019-05-16
申请号：US15867437
申请日：2018-01-10
发明人： Daniel Beylkin , Kenneth L. Ho , Sagar Vinodbhai Trivedi , Fangbo Xu , Junjiang Lei , Danping Peng
IPC分类号： G05B19/4097 , G06F17/50 , G03F1/70 , G03F1/36 , G03F1/24
摘要： Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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公开(公告)号：US11747786B2
公开(公告)日：2023-09-05
申请号：US17750828
申请日：2022-05-23
发明人： Danping Peng , Junjiang Lei , Daniel Beylkin , Kenneth Lik Kin Ho , Sagar Trivedi , Fangbo Xu
IPC分类号： G06F30/392 , G06F30/3308 , G06F30/367 , G03F1/70 , G03F1/36 , G03F1/24 , G05B19/4097 , G21K5/00 , G06F111/20 , G06F119/18
CPC分类号： G05B19/4097 , G03F1/24 , G03F1/36 , G03F1/70 , G06F30/392 , G05B2219/35012 , G05B2219/45027 , G05B2219/45028 , G05B2219/45031 , G06F30/3308 , G06F30/367 , G06F2111/20 , G06F2119/18 , G21K5/00
摘要： Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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公开(公告)号：US20200293023A1
公开(公告)日：2020-09-17
申请号：US16889514
申请日：2020-06-01
发明人： Danping Peng , Junjiang Lei , Daniel Beylkin , Kenneth Lik Kin Ho , Sagar Trivedi , Fangbo Xu
IPC分类号： G05B19/4097 , G03F1/70 , G03F1/36 , G03F1/24 , G06F30/392
摘要： Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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公开(公告)号：US20230384665A1
公开(公告)日：2023-11-30
申请号：US18447425
申请日：2023-08-10
发明人： Kenji Yamazoe , Junjiang Lei , Danping Peng
CPC分类号： G03F1/70 , G06F17/16 , G03F1/44 , G03F1/42 , G03F7/2004
摘要： Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.
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公开(公告)号：US11829066B2
公开(公告)日：2023-11-28
申请号：US17240265
申请日：2021-04-26
发明人： Kenji Yamazoe , Junjiang Lei , Danping Peng
CPC分类号： G03F1/70 , G03F1/42 , G03F1/44 , G03F7/2004 , G06F17/16
摘要： Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.
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公开(公告)号：US10915090B2
公开(公告)日：2021-02-09
申请号：US16889514
申请日：2020-06-01
发明人： Danping Peng , Junjiang Lei , Daniel Beylkin , Kenneth Lik Kin Ho , Sagar Trivedi , Fangbo Xu
IPC分类号： G06F30/392 , G06F30/30 , G06F30/33 , G03F1/00 , G05B19/4097 , G03F1/70 , G03F1/36 , G03F1/24 , G06F111/20 , G06F119/18
摘要： Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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公开(公告)号：US20220291659A1
公开(公告)日：2022-09-15
申请号：US17750828
申请日：2022-05-23
发明人： Danping Peng , Junjiang Lei , Daniel Beylkin , Kenneth Lik Kin Ho , Sagar Trivedi , Fangbo Xu
IPC分类号： G05B19/4097 , G03F1/70 , G03F1/36 , G03F1/24 , G06F30/392
摘要： Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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公开(公告)号：US11340584B2
公开(公告)日：2022-05-24
申请号：US17170389
申请日：2021-02-08
发明人： Danping Peng , Junjiang Lei , Daniel Beylkin , Kenneth Lik Kin Ho , Sagar Trivedi , Fangbo Xu
IPC分类号： G05B19/4097 , G06F30/392 , G06F30/3308 , G06F30/367 , G03F1/70 , G03F1/36 , G03F1/24 , G06F111/20 , G06F119/18 , G21K5/00
摘要： Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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公开(公告)号：US20210247689A1
公开(公告)日：2021-08-12
申请号：US17240265
申请日：2021-04-26
发明人： Kenji Yamazoe , Junjiang Lei , Danping Peng
摘要： Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.
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公开(公告)号：US20210181713A1
公开(公告)日：2021-06-17
申请号：US17170389
申请日：2021-02-08
发明人： Danping Peng , Junjiang Lei , Daniel Beylkin , Kenneth Lik Kin Ho , Sagar Trivedi , Fangbo Xu
IPC分类号： G05B19/4097 , G03F1/70 , G03F1/36 , G03F1/24 , G06F30/392
摘要： Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.
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