公开(公告)号：US20230059026A1

公开(公告)日：2023-02-23

申请号：US17977317

申请日：2022-10-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H01L45/00 ,  H01L21/321 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3105 ,  H01L27/24

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

公开(公告)号：US11049767B2

公开(公告)日：2021-06-29

申请号：US16584594

申请日：2019-09-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsai-Ming Huang ,  Wei-Chieh Huang ,  Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Che Chung ,  Chin-Wei Liang ,  Ching-Sen Kuo ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Sheng-Chau Chen

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/544 ,  H01L23/522

摘要： In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

公开(公告)号：US20200152863A1

公开(公告)日：2020-05-14

申请号：US16741250

申请日：2020-01-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen

IPC分类号： H01L43/12 ,  H01L43/08

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.

公开(公告)号：US20240334847A1

公开(公告)日：2024-10-03

申请号：US18738161

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H10N70/00 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8418 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76879 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

公开(公告)号：US20220216398A1

公开(公告)日：2022-07-07

申请号：US17705717

申请日：2022-03-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen

IPC分类号： H01L43/12 ,  H01L43/08

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.

公开(公告)号：US10910260B2

公开(公告)日：2021-02-02

申请号：US16664455

申请日：2019-10-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Chieh Huang ,  Chin-Wei Liang ,  Feng-Jia Shiu ,  Hsia-Wei Chen ,  Jieh-Jang Chen ,  Ching-Sen Kuo

IPC分类号： H01L21/768 ,  H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  H01L21/3105 ,  H01L21/66 ,  H01L43/12

摘要： A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.

公开(公告)号：US11489115B2

公开(公告)日：2022-11-01

申请号：US17306626

申请日：2021-05-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L45/00 ,  H01L21/321 ,  H01L21/311 ,  H01L21/285 ,  H01L27/24

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

公开(公告)号：US20210257548A1

公开(公告)日：2021-08-19

申请号：US17306626

申请日：2021-05-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H01L45/00 ,  H01L21/321 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3105 ,  H01L27/24

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

公开(公告)号：US10535815B2

公开(公告)日：2020-01-14

申请号：US15834670

申请日：2017-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen

IPC分类号： H01L43/12 ,  H01L43/08

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming an opening with a tapered profile in a first material layer. An upper width of the opening is greater than a bottom width of opening. The method also includes forming a second material layer in the opening and forming a hard mask to cover a portion of the second material layer. The hard mask aligns to the opening and has a width smaller than the upper width of the opening. The method also includes etching the second material layer by using the hard mask as an etch mask to form an upper portion of a feature with a tapered profile.

公开(公告)号：US10439135B2

公开(公告)日：2019-10-08

申请号：US15884505

申请日：2018-01-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H01L21/768 ,  H01L45/00 ,  H01L21/321 ,  H01L21/311 ,  H01L21/285 ,  H01L21/3105

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.