公开(公告)号：US20190252193A1

公开(公告)日：2019-08-15

申请号：US16396429

申请日：2019-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

IPC分类号： H01L21/283 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/308

摘要： First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

公开(公告)号：US10276392B2

公开(公告)日：2019-04-30

申请号：US15642559

申请日：2017-07-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

IPC分类号： H01L21/306 ,  H01L21/283 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

摘要： First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

公开(公告)号：US11387105B2

公开(公告)日：2022-07-12

申请号：US17001382

申请日：2020-08-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

IPC分类号： H01L21/306 ,  H01L21/283 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

摘要： First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

公开(公告)号：US20170194443A1

公开(公告)日：2017-07-06

申请号：US15079436

申请日：2016-03-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

IPC分类号： H01L29/423 ,  H01L21/308 ,  H01L21/283 ,  H01L21/306

CPC分类号： H01L21/283 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/823456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

公开(公告)号：US11961738B2

公开(公告)日：2024-04-16

申请号：US17175366

申请日：2021-02-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chin-Ta Chen ,  Hua-Tai Lin ,  Han-Wei Wu ,  Jiann-Yuan Huang

IPC分类号： H01L21/027 ,  H01L21/3213

CPC分类号： H01L21/0274 ,  H01L21/32139

摘要： In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

公开(公告)号：US09711604B1

公开(公告)日：2017-07-18

申请号：US15079436

申请日：2016-03-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

IPC分类号： H01L21/308 ,  H01L29/423 ,  H01L21/306 ,  H01L21/283

CPC分类号： H01L21/283 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/823456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

公开(公告)号：US11804410B2

公开(公告)日：2023-10-31

申请号：US16810607

申请日：2020-03-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-De Ho ,  Han-Wei Wu ,  Pei-Sheng Tang ,  Meng-Jung Lee ,  Hua-Tai Lin ,  Szu-Ping Tung ,  Lan-Hsin Chiang

IPC分类号： H01L21/66 ,  H01L21/67

CPC分类号： H01L22/12 ,  H01L21/67288

摘要： A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

公开(公告)号：US10755936B2

公开(公告)日：2020-08-25

申请号：US16396429

申请日：2019-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

IPC分类号： H01L21/306 ,  H01L21/283 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

摘要： First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

公开(公告)号：US20170309718A1

公开(公告)日：2017-10-26

申请号：US15642559

申请日：2017-07-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jin-Dah Chen ,  Ming-Feng Shieh ,  Han-Wei Wu ,  Yu-Hsien Lin ,  Po-Chun Liu ,  Stan Chen

IPC分类号： H01L29/423 ,  H01L21/308 ,  H01L21/306 ,  H01L21/283

CPC分类号： H01L21/283 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/823456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.