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    MULTI-LEVEL STACKING OF WAFERS AND CHIPS
    1.
    发明申请
    MULTI-LEVEL STACKING OF WAFERS AND CHIPS 有权

    公开(公告)号：US20240379614A1

    公开(公告)日：2024-11-14

    申请号：US18782253

    申请日：2024-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

    IPC: H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065

    Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

    MULTI-LEVEL STACKING OF WAFERS AND CHIPS
    2.
    发明申请
    MULTI-LEVEL STACKING OF WAFERS AND CHIPS 有权

    公开(公告)号：US20210375819A1

    公开(公告)日：2021-12-02

    申请号：US17074107

    申请日：2020-10-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

    Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

    Through-Dielectric Vias for Direct Connection and Method Forming Same
    7.
    发明申请
    Through-Dielectric Vias for Direct Connection and Method Forming Same 有权

    公开(公告)号：US20220262766A1

    公开(公告)日：2022-08-18

    申请号：US17229283

    申请日：2021-04-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Chuan-An Cheng ,  Sung-Feng Yeh ,  Chih-Chia Hu

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00

    Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

    Semiconductor structure and method manufacturing the same
    8.
    发明授权
    Semiconductor structure and method manufacturing the same 有权

    公开(公告)号：US11164848B2

    公开(公告)日：2021-11-02

    申请号：US16737869

    申请日：2020-01-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chuan-An Cheng

    IPC: H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L23/31

    Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

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