Invention Grant
- Patent Title: Multi-level stacking of wafers and chips
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Application No.: US17074107Application Date: 2020-10-19
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Publication No.: US11721663B2Publication Date: 2023-08-08
- Inventor: Ming-Fa Chen , Cheng-Feng Chen , Sung-Feng Yeh , Chuan-An Cheng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/28
- IPC: H01L23/28 ; H01L23/367 ; H01L25/065 ; H01L23/00 ; H01L25/00 ; H01L21/78

Abstract:
In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.
Public/Granted literature
- US20210375819A1 MULTI-LEVEL STACKING OF WAFERS AND CHIPS Public/Granted day:2021-12-02
Information query
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