公开(公告)号：US11171235B2

公开(公告)日：2021-11-09

申请号：US16865423

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chang Wei ,  Chia-Lin Hsu ,  Hsien-Ming Lee ,  Ji-Cheng Chen

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L27/12

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.

公开(公告)号：US20200266297A1

公开(公告)日：2020-08-20

申请号：US16865423

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chang Wei ,  Chia-Lin Hsu ,  Hsien-Ming Lee ,  Ji-Cheng Chen

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate within a first region and includes a first gate electrode. The first gate electrode includes a first filter layer between and in contact with a first conductive layer and a second conductive layer. The second transistor is disposed on the substrate within a second region and includes a second gate electrode. The second gate electrode includes a second filter layer between and in contact with a third conductive layer and a fourth conductive layer. The first transistor and the second transistor have a same conductive type, a first threshold voltage of the first transistor is lower than a second threshold voltage of the second transistor, and a first thickness of the first filter layer is larger than a second thickness of the second filter layer.

公开(公告)号：US11699618B2

公开(公告)日：2023-07-11

申请号：US16991665

申请日：2020-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Yi Lee ,  Chia-Lin Hsu

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/76832 ,  H01L23/53295 ,  H01L21/02247 ,  H01L21/02252

Abstract: The present disclosure describes a method for forming a nitrogen-rich protective layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

公开(公告)号：US10978350B2

公开(公告)日：2021-04-13

申请号：US16698336

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Chia-Lin Hsu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/20 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L29/51 ,  H01L29/06 ,  H01L23/532 ,  H01L29/49 ,  H01L29/78 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: Metal gate formation methods are disclosed herein for providing metal gates with low work function to enhance semiconductor field effect transistor performance. An exemplary method includes forming a gate dielectric layer on a substrate and a barrier layer over the gate dielectric layer. An outer surface of the barrier layer is treated to increase its roughness. After the outer surface of the barrier layer is roughened, a metal layer is deposited over the barrier layer.

公开(公告)号：US20200098641A1

公开(公告)日：2020-03-26

申请号：US16698336

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Chia-Lin Hsu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/20 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L29/51 ,  H01L29/06 ,  H01L23/532 ,  H01L29/49 ,  H01L29/78 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.

公开(公告)号：US20190067117A1

公开(公告)日：2019-02-28

申请号：US16101667

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Chia-Lin Hsu

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L29/423 ,  H01L29/20 ,  H01L29/51 ,  H01L29/49 ,  H01L23/532 ,  H01L29/06

Abstract: A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.

公开(公告)号：US10049940B1

公开(公告)日：2018-08-14

申请号：US15800164

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Chia-Lin Hsu

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/20 ,  H01L21/28 ,  H01L21/02 ,  H01L21/283 ,  H01L29/06 ,  H01L23/532 ,  H01L29/49

Abstract: A method of forming a semiconductor device includes receiving a structure having a substrate, a gate trench over the substrate, and a dielectric layer over the substrate and surrounding the gate trench. The method further includes forming a gate dielectric layer in the gate trench, forming a barrier layer in the gate trench and over the gate dielectric layer, and treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer. The method further includes forming an n-type work function metal layer over the treated barrier layer.

公开(公告)号：US20170250279A1

公开(公告)日：2017-08-31

申请号：US15054080

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chang Wei ,  Chia-Lin Hsu ,  Hsien-Ming Lee ,  Ji-Cheng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.