公开(公告)号：US20210193832A1

公开(公告)日：2021-06-24

申请号：US17195146

申请日：2021-03-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Xi-Zong Chen ,  Te-Chih Hsiung ,  Cha-Hsin Chao ,  Yi-Wei Chiu

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/311 ,  H01L21/027 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84

摘要： A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

公开(公告)号：US20200050103A1

公开(公告)日：2020-02-13

申请号：US16657551

申请日：2019-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Xi-Zong Chen ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Chih-Hsuan Lin

IPC分类号： G03F7/004 ,  G03F7/20 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

摘要： The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.

公开(公告)号：US11424364B2

公开(公告)日：2022-08-23

申请号：US17195146

申请日：2021-03-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Xi-Zong Chen ,  Te-Chih Hsiung ,  Cha-Hsin Chao ,  Yi-Wei Chiu

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/311 ,  H01L21/027 ,  H01L29/08 ,  H01L23/535 ,  H01L21/8238 ,  H01L21/84

摘要： A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.

公开(公告)号：US11088025B2

公开(公告)日：2021-08-10

申请号：US16883508

申请日：2020-05-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yun-Yu Hsieh ,  Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/417 ,  H01L21/311 ,  H01L23/485

摘要： A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.

公开(公告)号：US10679896B2

公开(公告)日：2020-06-09

申请号：US16140201

申请日：2018-09-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yun-Yu Hsieh ,  Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/417 ,  H01L21/311 ,  H01L23/485

摘要： A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a first conductive region within the first ILD layer, selectively removing a portion of the first conductive region to form a concave top surface of the first conductive region. The method also includes forming a second ILD layer over the first ILD layer and forming a second conductive region within the second ILD layer and on the concave top surface. The concave top surface provides a large contact area, and hence reduced contact resistance between the first and second conductive regions.

公开(公告)号：US11232978B2

公开(公告)日：2022-01-25

申请号：US16845415

申请日：2020-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3115 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

摘要： In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

公开(公告)号：US20210366770A1

公开(公告)日：2021-11-25

申请号：US17397621

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yun-Yu Hsieh ,  Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/417 ,  H01L21/311 ,  H01L23/485

摘要： A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.

公开(公告)号：US20210028062A1

公开(公告)日：2021-01-28

申请号：US17066751

申请日：2020-10-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L23/485 ,  H01L23/528 ,  H01L29/06

摘要： A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

公开(公告)号：US20200243378A1

公开(公告)日：2020-07-30

申请号：US16845415

申请日：2020-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/3115 ,  H01L21/02

摘要： In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.

公开(公告)号：US10651079B2

公开(公告)日：2020-05-12

申请号：US16222488

申请日：2018-12-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jeng Chang Her ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3115 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

摘要： In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.