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公开(公告)号：US20190384185A1
公开(公告)日：2019-12-19
申请号：US16008267
申请日：2018-06-14
发明人： Tseng Chin Lo , Bo-Sen Chang , Yueh-Yi Chen , Chih-Ting Sun , Ying-Jung Chen , Kung-Cheng Lin , Meng Lin Chang
摘要： Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
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公开(公告)号：US11309307B2
公开(公告)日：2022-04-19
申请号：US16946160
申请日：2020-06-08
发明人： Tseng Chin Lo , Molly Chang , Ya-Wen Tseng , Chih-Ting Sun , Zi-Kuan Li , Bo-Sen Chang , Geng-He Lin
IPC分类号： H01L21/66 , H01L27/02 , G06F30/392 , H01L21/027 , H01L21/8234 , H01L27/11
摘要： Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
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公开(公告)号：US20210278771A1
公开(公告)日：2021-09-09
申请号：US17327990
申请日：2021-05-24
发明人： Tseng Chin Lo , Bo-Sen Chang , Yueh-Yi Chen , Chih-Ting Sun , Ying-Jung Chen , Kung-Cheng Lin , Meng Lin Chang
摘要： Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
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公开(公告)号：US10679980B2
公开(公告)日：2020-06-09
申请号：US16540809
申请日：2019-08-14
发明人： Tseng Chin Lo , Molly Chang , Ya-Wen Tseng , Chih-Ting Sun , Zi-Kuan Li , Bo-Sen Chang , Geng-He Lin
IPC分类号： H01L21/00 , H01L27/02 , H01L21/66 , G06F30/392 , H01L21/027 , H01L21/8234 , H01L27/11
摘要： Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
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公开(公告)号：US20230359131A1
公开(公告)日：2023-11-09
申请号：US18357220
申请日：2023-07-24
发明人： Tseng Chin Lo , Bo-Sen Chang , Yueh-Yi Chen , Chih-Ting Sun , Ying-Jung Chen , Kung-Cheng Lin , Meng Lin Chang
CPC分类号： G03F7/70633 , H01L22/12 , H01L29/785 , G03F9/7084
摘要： Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
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公开(公告)号：US11776948B2
公开(公告)日：2023-10-03
申请号：US17659645
申请日：2022-04-18
发明人： Tseng Chin Lo , Molly Chang , Ya-Wen Tseng , Chih-Ting Sun , Zi-Kuan Li , Bo-Sen Chang , Geng-He Lin
IPC分类号： H01L27/02 , H01L21/66 , G06F30/392 , H10B10/00 , H01L21/027 , H01L21/8234
CPC分类号： H01L27/0207 , G06F30/392 , H01L21/0274 , H01L21/8234 , H01L22/12 , H01L22/30 , H10B10/00 , H01L22/10 , H01L22/14 , H01L22/34
摘要： Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
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公开(公告)号：US11762302B2
公开(公告)日：2023-09-19
申请号：US17327990
申请日：2021-05-24
发明人： Tseng Chin Lo , Bo-Sen Chang , Yueh-Yi Chen , Chih-Ting Sun , Ying-Jung Chen , Kung-Cheng Lin , Meng Lin Chang
CPC分类号： G03F7/70633 , G03F9/7084 , H01L22/12 , H01L29/785
摘要： Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
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公开(公告)号：US11016398B2
公开(公告)日：2021-05-25
申请号：US16008267
申请日：2018-06-14
发明人： Tseng Chin Lo , Bo-Sen Chang , Yueh-Yi Chen , Chih-Ting Sun , Ying-Jung Chen , Kung-Cheng Lin , Meng Lin Chang
摘要： Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
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公开(公告)号：US10388645B2
公开(公告)日：2019-08-20
申请号：US16047827
申请日：2018-07-27
发明人： Tseng Chin Lo , Molly Chang , Ya-Wen Tseng , Chih-Ting Sun , Zi-Kuan Li , Bo-Sen Chang , Geng-He Lin
IPC分类号： H01L21/00 , H01L27/02 , G06F17/50 , H01L21/027 , H01L21/8234 , H01L27/11 , H01L21/66
摘要： Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
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公开(公告)号：US10283496B2
公开(公告)日：2019-05-07
申请号：US15484628
申请日：2017-04-11
发明人： Tseng Chin Lo , Molly Chang , Ya-Wen Tseng , Chih-Ting Sun , Zi-Kuan Li , Bo-Sen Chang , Geng-He Lin
IPC分类号： H01L21/00 , H01L27/02 , G06F17/50 , H01L21/027 , H01L21/8234 , H01L21/66 , H01L27/11
摘要： Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
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