- 专利标题: Integrated circuit overlay test patterns and method thereof
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申请号: US16008267申请日: 2018-06-14
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公开(公告)号: US11016398B2公开(公告)日: 2021-05-25
- 发明人: Tseng Chin Lo , Bo-Sen Chang , Yueh-Yi Chen , Chih-Ting Sun , Ying-Jung Chen , Kung-Cheng Lin , Meng Lin Chang
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Haynes and Boone, LLP
- 主分类号: G03F7/20
- IPC分类号: G03F7/20 ; H01L29/78 ; H01L21/66 ; G03F9/00
摘要:
Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
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