INTEGRATED CIRCUIT WITH A GALVANICALLY-ISOLATED COMMUINCATION CHANNEL USING A BACK-SIDE ETCHED CHANNEL

    公开(公告)号:US20220406956A1

    公开(公告)日:2022-12-22

    申请号:US17680981

    申请日:2022-02-25

    Abstract: An integrated circuit (IC) includes a substrate having a first surface and a second surface opposite the first surface. The substrate has a first region containing a first circuit and a second region containing a second circuit. The first circuit operates at a first supply voltage. The second circuit operates at a second supply voltage. The second supply voltage is higher than the first supply voltage. The IC includes a through wafer trench (TWT) extending from the first surface of the substrate to the second surface of the semiconductor substrate. The TWT separates the first region from the second region. A dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region is continuous over the first region, the second region, and the TWT. A non-galvanic communication channel is between the first and second circuits.

    MULTI-PHASE OSCILLATORS
    4.
    发明申请

    公开(公告)号:US20230035350A1

    公开(公告)日:2023-02-02

    申请号:US17389935

    申请日:2021-07-30

    Abstract: An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.

    POWER AMPLIFIER WITH SERIES TRANSFORMER COMBINERS AND HARMONIC TUNING

    公开(公告)号:US20220173700A1

    公开(公告)日:2022-06-02

    申请号:US17109763

    申请日:2020-12-02

    Abstract: A system includes a first differential amplifier and a first transformer with a primary coil coupled to an output of the first differential amplifier and with a secondary coil coupled to a load. The system also includes a second differential amplifier and a second transformer with a primary coil coupled to an output of the second differential amplifier and with a secondary coil coupled in series with the secondary coil of the first transformer. The system also includes a tuning network coupled to a center tap node between the secondary coil of the first transformer and the secondary coil of the second transformer.

    TRANSMIT AND RECEIVE SWITCH WITH TRANSFORMER

    公开(公告)号:US20240113739A1

    公开(公告)日:2024-04-04

    申请号:US17957253

    申请日:2022-09-30

    CPC classification number: H04B1/18 H03H2/008 H04B1/0078 H01Q23/00

    Abstract: In examples, an electronic device includes an antenna and a transmitter line. The transmitter line includes a double-tuned transformer having first and second windings, the first winding having first and second ends, the second winding having third and fourth ends, and the third end coupled to the antenna. The transmitter line includes a first capacitor coupled between the first and second ends. The transmitter line also includes a second capacitor coupled between the third and fourth ends, and a switch coupled between the first end and a reference terminal.

    LOW-FREQUENCY COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ULTRASONIC TRANSDUCER

    公开(公告)号:US20230271222A1

    公开(公告)日:2023-08-31

    申请号:US17682576

    申请日:2022-02-28

    CPC classification number: B06B1/0292

    Abstract: In accordance with at least one example of the description, a device includes a substrate and a linear array of transducer elements across the substrate and forming a cavity region. The cavity region is bounded by a first termination region and a second termination region. The linear array of transducer elements includes a transducer element having a front-end-of-line (FEOL) portion that is formed by a FEOL process and a back-end-of-line (BEOL) portion that is formed by an n-layer BEOL process. The BEOL portion of the transducer element includes a ferroelectric capacitor and a conductive element. The conductive element is formed by metal layer-n of the n-layer BEOL process, where n denotes an integer greater than 3.

    RADIATOR LAYERS FOR ULTRASONIC TRANSDUCERS
    9.
    发明公开

    公开(公告)号:US20240113063A1

    公开(公告)日:2024-04-04

    申请号:US17957446

    申请日:2022-09-30

    Abstract: In examples, a semiconductor die comprises a semiconductor substrate having a surface, the surface having first and second surface portions, and a radiator layer on the surface. The radiator layer comprises a metal member having a first metal member portion above the first surface portion and a second metal member portion above the second surface portion, a first distance between the first metal member portion and the first surface portion, and a second distance between the second metal member portion and the second surface portion, the first distance less than the second distance. The radiator layer includes first and second electrodes. The radiator layer includes a piezoelectric layer extending along a length of the radiator layer and on each of the first and second electrodes, the piezoelectric layer between the first and second metal members and the semiconductor substrate.

    MULTI-TURN DISTRIBUTED ACTIVE TRANSFORMER POWER COMBINER

    公开(公告)号:US20230317348A1

    公开(公告)日:2023-10-05

    申请号:US17708246

    申请日:2022-03-30

    CPC classification number: H01F27/2804 H01L28/10 H01F2027/2809

    Abstract: An apparatus includes a first primary coil, a second primary coil, and a secondary coil. The first and second primary coils each include a first, second, and third portion. The secondary coil includes a first and second portion in a first wafer layer, which are coupled together by a bridge in a second wafer layer. The second portion of the first primary coil is nested inside the first portion of the secondary coil in the first wafer layer. The second portion of the second primary coil is nested inside the second portion of the secondary coil in the first wafer layer. At least parts of the first and third portions of the first primary coil are adjacent the second portion of the secondary coil, and at least parts of the first and third portions of the second primary coil are adjacent the first portion of the secondary coil.

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