AGING COMPENSATION OF A FERROELECTRIC PIEZOELECTRIC SHOCK SENSOR

    公开(公告)号:US20240077514A1

    公开(公告)日:2024-03-07

    申请号:US18507150

    申请日:2023-11-13

    CPC classification number: G01P21/00 G01P15/09

    Abstract: A method comprises receiving a signal from a piezoelectric device and receiving a measurement of a temperature of the piezoelectric device. The method further comprises reading a first parameter from a memory, in which the first parameter depends on the temperature and relates the signal to an acceleration value and reading a second parameter from the memory, in which the second parameter represents a degree of drift of the piezoelectric device at the temperature. The method further comprises determining an acceleration of the piezoelectric device based on the signal, the first parameter, and the second parameter.

    AGING COMPENSATION OF A FERROELECTRIC PIEZOELECTRIC SHOCK SENSOR

    公开(公告)号:US20210199688A1

    公开(公告)日:2021-07-01

    申请号:US16856488

    申请日:2020-04-23

    Abstract: A method includes measuring a first signal from a set of pyroelectric devices at a first temperature and measuring a second signal from a set of piezoelectric devices at a first acceleration. The method also includes measuring a third signal from the set of pyroelectric devices at a second temperature and measuring a fourth signal from the set of piezoelectric devices at a second acceleration. The method further includes adjusting a piezoelectric calibration using the first, second, third, and fourth signals.

    INTEGRATED CIRCUIT WITH A GALVANICALLY-ISOLATED COMMUINCATION CHANNEL USING A BACK-SIDE ETCHED CHANNEL

    公开(公告)号:US20220406956A1

    公开(公告)日:2022-12-22

    申请号:US17680981

    申请日:2022-02-25

    Abstract: An integrated circuit (IC) includes a substrate having a first surface and a second surface opposite the first surface. The substrate has a first region containing a first circuit and a second region containing a second circuit. The first circuit operates at a first supply voltage. The second circuit operates at a second supply voltage. The second supply voltage is higher than the first supply voltage. The IC includes a through wafer trench (TWT) extending from the first surface of the substrate to the second surface of the semiconductor substrate. The TWT separates the first region from the second region. A dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region is continuous over the first region, the second region, and the TWT. A non-galvanic communication channel is between the first and second circuits.

    THROUGH WAFER ISOLATION ELEMENT BACKSIDE PROCESSING

    公开(公告)号:US20220359268A1

    公开(公告)日:2022-11-10

    申请号:US17683201

    申请日:2022-02-28

    Abstract: Disclosed herein is an integrated circuit (IC) comprising a semiconductor wafer, a dielectric layer, and an isolation element. The semiconductor wafer has a first wafer portion and a second wafer portion each extending from a frontside surface to a backside surface. The dielectric layer interfaces with the first wafer portion and with the second wafer portion each on the frontside surface. The isolation element has an isolation dielectric material, and the isolation element extends between a first side surface of the first wafer portion and a second side surface of the second wafer portion and from an extension plane of the frontside surface to an extension plane of the backside surface. Also disclosed herein is a system comprising the IC and a package substrate coupled to the IC.

    MEMS ENCAPSULATION EMPLOYING LOWER PRESSURE AND HIGHER PRESSURE DEPOSITION PROCESSES

    公开(公告)号:US20220324702A1

    公开(公告)日:2022-10-13

    申请号:US17514282

    申请日:2021-10-29

    Abstract: A micro-electromechanical system (MEMS) device includes a moveable element within a cavity. The MEMS device also includes a first layer over the cavity, the first layer having a first hole and a second hole. The first hole has a first diameter. The second hole has a second diameter. The second diameter is larger than the first diameter, and the second hole is farther from the moveable element than the first hole. The first hole is sealed with a first dielectric material. The second hole is sealed with a second dielectric material. The cavity filled with a gas at a pressure of at least approximately 10 torr.

    INTEGRATED CIRCUIT BACKSIDE RADIATION/RESONATOR

    公开(公告)号:US20220406738A1

    公开(公告)日:2022-12-22

    申请号:US17732822

    申请日:2022-04-29

    Abstract: An integrated circuit (IC) includes a semiconductor substrate having a first surface and a second surface opposite the first surface. A through wafer trench (TWT) extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate. Dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region has a conductive transmit patch. An antenna is formed, at least in part, by the dielectric material in the TWT and the transmit patch in the interconnect region. The antenna is configured to transmit or receive electromagnetic radiation between the transmit patch and the second surface of the semiconductor substrate through the dielectric material within the trench.

    Technique for GaN Epitaxy on Insulating Substrates

    公开(公告)号:US20220246423A1

    公开(公告)日:2022-08-04

    申请号:US17588589

    申请日:2022-01-31

    Abstract: A method includes depositing a first epitaxial layer of an aluminum gallium nitride (AlGaN) material onto a preliminary substrate and polishing the first layer's surface. Ions are implanted beneath the surface, which is bonded to a seed insulating substrate. Annealing is performed, resulting in second epitaxial layer on preliminary substrate and third epitaxial layer on seed insulating substrate. Third layer's surface is polished to obtain a seed wafer. In some implementations, a fourth epitaxial layer of a second AlGaN material is deposited onto surface of third layer. Fourth layer's surface is polished, and ions are implanted beneath the surface, which is bonded to a product insulating substrate. Annealing is performed, resulting in fifth epitaxial layer on seed insulating substrate and sixth epitaxial layer on product insulating substrate. The sixth layer can be used to obtain an AlGaN product, and the fifth layer can be reused to fabricate additional AlGaN products.

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