公开(公告)号：US20230411262A1

公开(公告)日：2023-12-21

申请号：US18335979

申请日：2023-06-15

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Lopez ,  Jonathan Noquil ,  Jose Carlos Arroyo ,  Makarand R. Kulkarni ,  Guangxu Li

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/565 ,  H01L2021/60022 ,  H01L23/49822 ,  H01L21/563

Abstract: An example microelectronics device package includes: a device mounting layer on an uppermost trace conductor layer on a device side surface of a package substrate, the uppermost trace conductor layer having a first pattern density. The device mounting layer includes a device connection conductor layer; a device mounting land conductor layer on the device connection conductor layer, the device mounting land conductor layer having device mounting land conductors directly contacting the conductors of the device connection conductor layer and having a second pattern density that is less than the first pattern density. A semiconductor die is flip chip mounted to the device mounting layer by solder joints between post connects extending from the semiconductor die and the device mounting land conductors. Mold compound covers the semiconductor die, and the device mounting layer, the mold compound is spaced from the uppermost trace conductor layer by the device mounting layer.

公开(公告)号：US20240096771A1

公开(公告)日：2024-03-21

申请号：US17946109

申请日：2022-09-16

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Lopez ,  Salvatore Pavone ,  Sreenivasan Koduri

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L23/49805 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/165 ,  H01L23/3738 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2224/95001

Abstract: An electronic device includes a multilevel metallization structure, a semiconductor die, and a package structure. The multilevel metallization structure has multiple levels of conductive metal traces and vias and polyimide insulator material, including a first level along a first side and a final level along a second side. The first level includes conductive metal leads with exposed surfaces along the first side, and the final level includes conductive metal pads with exposed surfaces along the second side. The semiconductor die is flip chip attached to the first side of the multilevel metallization structure with conductive features connected to respective conductive metal pads of the final level of the multilevel metallization structure, and the package structure encloses the semiconductor die and portions of the first side of the multilevel metallization structure.

公开(公告)号：US20250140769A1

公开(公告)日：2025-05-01

申请号：US18498092

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yunyi Gong ,  Kenji Otake ,  Hidetoshi Inoue ,  Sombuddha Chakraborty ,  Jonathan Montoya ,  Osvaldo Lopez

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373

Abstract: A packaged integrated circuit (IC) includes a package substrate and an IC on the package substrate. A first material is on the package substrate and encapsulates the IC. An inductor is coupled to the package substrate. A heat sink includes a second material. The heat sink is coupled to the IC. A third material is on the first material and encapsulates the inductor and at least part of the heat sink. The second material has a higher thermal conductivity than the first and third materials.